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Message-ID: <20130402175405.GA6435@jshin-Toonie>
Date: Tue, 2 Apr 2013 12:54:05 -0500
From: Jacob Shin <jacob.shin@....com>
To: Ingo Molnar <mingo@...hat.com>,
Stephane Eranian <eranian@...gle.com>,
Peter Zijlstra <a.p.zijlstra@...llo.nl>, <x86@...nel.org>
CC: Thomas Gleixner <tglx@...utronix.de>,
"H. Peter Anvin" <hpa@...or.com>, Jiri Olsa <jolsa@...hat.com>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/3] perf, amd: Support for Family 16h L2I Performance
Counters
On Wed, Mar 27, 2013 at 06:07:01PM -0500, Jacob Shin wrote:
> Upcoming AMD Family 16h Processors provide 4 new performance counters
> to count L2 related events. Similar to northbridge counters, these new
> counters are shared across multiple CPUs that share the same L2 cache.
> This patchset adds support for these new counters and enforces sharing
> by leveraging the existing sharing logic used for the northbridge
> counters.
Ingo, please consider commiting to perf/core for 3.10. This patchset
is very similar to our northbridge counter support that went into 3.9:
https://lkml.org/lkml/2013/2/18/81
This series adds support for yet another set of new counters.
Thank you,
>
> Jacob Shin (3):
> perf, amd: Further generalize NB event constraints handling logic
> perf, x86: Allow for multiple kfree_on_online pointers
> perf, amd: Enable L2I performance counters on AMD Family 16h
>
> arch/x86/include/asm/cpufeature.h | 2 +
> arch/x86/include/asm/perf_event.h | 4 +
> arch/x86/include/uapi/asm/msr-index.h | 4 +
> arch/x86/kernel/cpu/perf_event.c | 7 +-
> arch/x86/kernel/cpu/perf_event.h | 11 +-
> arch/x86/kernel/cpu/perf_event_amd.c | 227 +++++++++++++++++++++++++-------
> arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
> 7 files changed, 199 insertions(+), 58 deletions(-)
>
> --
> 1.7.9.5
>
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