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Message-ID: <515F3E96.4040307@free-electrons.com>
Date: Fri, 05 Apr 2013 23:13:58 +0200
From: Gregory CLEMENT <gregory.clement@...e-electrons.com>
To: Arnd Bergmann <arnd@...db.de>
CC: Lior Amsalem <alior@...vell.com>, Andrew Lunn <andrew@...n.ch>,
Ike Pan <ike.pan@...onical.com>,
Grant Likely <grant.likely@...retlab.ca>,
David Marlin <dmarlin@...hat.com>,
Yehuda Yitschak <yehuday@...vell.com>,
Tawfik Bayouk <tawfik@...vell.com>,
Dan Frazier <dann.frazier@...onical.com>,
Eran Ben-Avi <benavi@...vell.com>,
Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
Leif Lindholm <leif.lindholm@....com>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Jason Cooper <jason@...edaemon.net>,
Nadav Haklai <nadavh@...vell.com>,
Jon Masters <jcm@...hat.com>,
devicetree-discuss@...ts.ozlabs.org,
Rob Herring <rob.herring@...xeda.com>,
linux-arm-kernel@...ts.infradead.org,
Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
Chris Van Hoof <vanhoof@...onical.com>,
Nicolas Pitre <nico@...xnic.net>, linux-kernel@...r.kernel.org,
Maen Suleiman <maen@...vell.com>,
Shadi Ammouri <shadi@...vell.com>,
Olof Johansson <olof@...om.net>
Subject: Re: [PATCH v2 2/9] arm: mvebu: Align the internal registers virtual
base to support LPAE
On 04/05/2013 10:50 PM, Arnd Bergmann wrote:
> On Friday 05 April 2013, Gregory CLEMENT wrote:
>> From: Lior Amsalem <alior@...vell.com>
>>
>> In order to be able to support he LPAE, the internal registers virtual
>> base must be aligned to 2MB.
>>
>> Signed-off-by: Lior Amsalem <alior@...vell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@...e-electrons.com>
>
> This is a surprising limitation. Can you extend the above text to go into more
> detail where that alignment requirement comes from?
>
The explanation I had was that in LPAE section size is 2MB, in earlyprintk we map
the internal registers and it must be section aligned.
> Arnd
>
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>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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