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Message-ID: <CABJ1b_RW=UUxmTrYOsx2wsDm1egs9DL3dWtat0--5kqec9-rQA@mail.gmail.com>
Date: Tue, 9 Apr 2013 11:25:41 +0200
From: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
To: Michal Bachraty <michal.bachraty@...eamunlimited.com>
Cc: grant.likely@...retlab.ca, rob.herring@...xeda.com,
rob@...dley.net, mturquette@...aro.org,
devicetree-discuss@...ts.ozlabs.org, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] clk: si5351: Add gapless tuning for SI5351 PLL
On Tue, Apr 9, 2013 at 10:26 AM, Michal Bachraty
<michal.bachraty@...eamunlimited.com> wrote:
> For gapless tuning, there is no need for PLL reset and clkout power-down
> when tuning output. "silabs,gapless-tuning" parameter enables gapless tuning
> for specific clock output.
Michal,
does gapless tuning have any constraints? Can we use it for all rate
changes or determine the
need for pll reset by rate offset?
Sebastian
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