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Message-ID: <DA5C8125AAC0C2489F8E8E003A30ECAA022E22@MB21.inbox01.com>
Date: Tue, 9 Apr 2013 23:49:35 +0000
From: Greg Veintimilla <gveintimilla@...ewave.com>
To: Sekhar Nori <nsekhar@...com>,
Prabhakar lad <prabhakar.csengg@...il.com>
CC: DLOS <davinci-linux-open-source@...ux.davincidsp.com>,
LKML <linux-kernel@...r.kernel.org>,
LAK <linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH v9 1/2] ARM: davinci: dm365: add support for v4l2 video
display
Please remove me from this list. Thanks
-----Original Message-----
From: davinci-linux-open-source-bounces+ttran=freewave.com@...ux.davincidsp.com [mailto:davinci-linux-open-source-bounces+ttran=freewave.com@...ux.davincidsp.com] On Behalf Of Sekhar Nori
Sent: Tuesday, April 09, 2013 5:48 AM
To: Prabhakar lad
Cc: DLOS; LKML; LAK
Subject: Re: [PATCH v9 1/2] ARM: davinci: dm365: add support for v4l2 video display
On 4/8/2013 2:47 PM, Prabhakar lad wrote:
> From: Lad, Prabhakar <prabhakar.csengg@...il.com>
>
> Create platform devices for various video modules like venc,osd, vpbe
> and v4l2 driver for dm365.
>
> Signed-off-by: Lad, Prabhakar <prabhakar.csengg@...il.com>
> Acked-by: Sekhar Nori <nsekhar@...com>
> ---
> diff --git a/arch/arm/mach-davinci/davinci.h
> b/arch/arm/mach-davinci/davinci.h index 12d544b..a9de512 100644
> --- a/arch/arm/mach-davinci/davinci.h
> +++ b/arch/arm/mach-davinci/davinci.h
> @@ -36,8 +36,13 @@
> #include <media/davinci/vpbe_osd.h>
>
> #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
> +#define SYSMOD_VDAC_CONFIG 0x2c
> #define SYSMOD_VIDCLKCTL 0x38
> #define SYSMOD_VPSS_CLKCTL 0x44
> +#define VPSS_VENCCLKEN_ENABLE BIT(3)
> +#define VPSS_DACCLKEN_ENABLE BIT(4)
> +#define VPSS_PLLC2SYSCLK5_ENABLE BIT(5)
> +
Prabhakar, I noticed it only after I applied these patches, but these bit definitions in between list of register offsets is distracting. Can you please move them down after the register offsets when you send the pull request? You can add a comment /* VPSS CLKCTL bit definitions */ before you start the bit definitions.
> #define SYSMOD_VDD3P3VPWDN 0x48
> #define SYSMOD_VSCLKDIS 0x6c
> #define SYSMOD_PUPDCTL1 0x7c
Thanks,
Sekhar
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