linux-kernel - [tip:perf/core] perf/x86: Add Sandy Bridge constraints for CYCLE

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Message-ID: <tip-f8378f5259647710f0b4ecb814b0a1b0d9040de0@git.kernel.org>
Date:	Wed, 10 Apr 2013 06:55:45 -0700
From:	tip-bot for Andi Kleen <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, eranian@...gle.com, hpa@...or.com,
	mingo@...nel.org, ak@...ux.intel.com, tglx@...utronix.de
Subject: [tip:perf/core] perf/x86:
  Add Sandy Bridge constraints for CYCLE_ACTIVITY.*

Commit-ID:  f8378f5259647710f0b4ecb814b0a1b0d9040de0
Gitweb:     http://git.kernel.org/tip/f8378f5259647710f0b4ecb814b0a1b0d9040de0
Author:     Andi Kleen <ak@...ux.intel.com>
AuthorDate: Fri, 8 Mar 2013 15:22:48 -0800
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 10 Apr 2013 15:00:07 +0200

perf/x86: Add Sandy Bridge constraints for CYCLE_ACTIVITY.*

Add CYCLE_ACTIVITY.CYCLES_NO_DISPATCH/CYCLES_L1D_PENDING constraints.

These recently documented events have restrictions to counter
0-3 and counter 2 respectively. The perf scheduler needs to know
that to schedule them correctly.

IvyBridge already has the necessary constraints.

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Cc: a.p.zijlstra@...llo.nl
Cc: Stephane Eranian <eranian@...gle.com>
Link: http://lkml.kernel.org/r/1362784968-12542-1-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index e84c4ba..2ad2374 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -109,6 +109,8 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 	INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
 	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
 	INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
+	INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
 	EVENT_CONSTRAINT_END
 };
 
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