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Message-ID: <20130416084418.GA30756@mudshark.cambridge.arm.com>
Date: Tue, 16 Apr 2013 09:44:18 +0100
From: Will Deacon <will.deacon@....com>
To: Colin Cross <ccross@...roid.com>
Cc: Rob Herring <robherring2@...il.com>,
lkml <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"rob.herring@...xeda.com" <rob.herring@...xeda.com>,
Anton Vorontsov <cbouatmailru@...il.com>,
Kees Cook <keescook@...omium.org>,
Tony Luck <tony.luck@...el.com>,
Catalin Marinas <Catalin.Marinas@....com>
Subject: Re: [RFC PATCH 1/3] pstore-ram: use write-combine mappings
On Tue, Apr 16, 2013 at 01:43:09AM +0100, Colin Cross wrote:
> On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring <robherring2@...il.com> wrote:
> > Exclusive accesses still have further restrictions. From section 3.4.5:
> >
> > • It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be
> > performed to a memory region
> > with the Device or Strongly-ordered memory attribute. Unless the
> > implementation documentation explicitly
> > states that LDREX and STREX operations to a memory region with the
> > Device or Strongly-ordered attribute are
> > permitted, the effect of such operations is UNPREDICTABLE.
> >
> >
> > Given that it is implementation defined, I don't see how Linux can rely
> > on that behavior.
>
> I see, the problem is that while noncached and writecombined appear to
> be similar mappings, noncached is mapped in PRRR to strongly-ordered,
> while writecombined is mapped to unbufferable normal memory.
>
> I think adding a wmb() to persistent_ram_write is going to be
> expensive on cpus with outer caches like the L2X0, where wmb() will
> result in a spinlock. Is there a real SoC where this doesn't work?
A real SoC where exclusives don't work to memory not mapped as normal? Take
your pick...
Will
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