linux-kernel - Re: [RFC PATCH 1/3] pstore-ram: use write-combine mappings

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Message-ID: <20130419095445.GG14496@n2100.arm.linux.org.uk>
Date:	Fri, 19 Apr 2013 10:54:45 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Colin Cross <ccross@...roid.com>
Cc:	Rob Herring <robherring2@...il.com>,
	Tony Luck <tony.luck@...el.com>,
	Kees Cook <keescook@...omium.org>,
	lkml <linux-kernel@...r.kernel.org>,
	Rob Herring <rob.herring@...xeda.com>,
	Anton Vorontsov <cbouatmailru@...il.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [RFC PATCH 1/3] pstore-ram: use write-combine mappings

On Tue, Apr 09, 2013 at 08:53:18PM -0700, Colin Cross wrote:
> On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring <robherring2@...il.com> wrote:
> > -       return ioremap(start, size);
> > +       return ioremap_wc(start, size);
> 
> ioremap_wc corresponds to MT_DEVICE_WC, which is still device memory,
> so I don't see how this helps solve the problem in the commit message.

In reality it isn't, because there's no such thing as "write combining
device memory" in the ARM memory model.

There are three major memory types: strongly ordered, device and normal
memory.  Only normal memory can be cached in any way, which includes
using write combining.

#define ioremap_wc(cookie,size) __arm_ioremap((cookie), (size), MT_DEVICE_WC)

        [MT_DEVICE_WC] = {      /* ioremap_wc */
                .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,

         *                      n       TR      IR      OR
         *   BUFFERABLE         001     10      00      00
         *   DEV_WC             001     10
(see arch/arm/mm/proc-v7-2level.S for the rest of the table and its
description.)

So, DEV_WC is an alias for BUFFERABLE, which is normal memory,
uncacheable in both inner and outer caches.  This means that at the
moment, ioremap_wc() memory has the same properties as system memory
- with all the out of ordering effects you get there.

I don't put any guarantee on this though - we may end up having to
change it if we find a SoC needing this to really be device memory...
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