linux-kernel - Re: [PATCH] ARM: mmc: bcm281xx SDHCI driver

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Message-ID: <518DC8E6.5000606@nvidia.com>
Date:	Fri, 10 May 2013 22:28:22 -0600
From:	Stephen Warren <swarren@...dia.com>
To:	Christian Daudt <csd@...adcom.com>
CC:	Grant Likely <grant.likely@...retlab.ca>,
	Rob Herring <rob.herring@...xeda.com>,
	Rob Landley <rob@...dley.net>,
	Russell King <linux@....linux.org.uk>,
	Chris Ball <cjb@...top.org>, Olof Johansson <olof@...om.net>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Wei WANG <wei_wang@...lsil.com.cn>,
	Ludovic Desroches <ludovic.desroches@...el.com>,
	Arnd Bergmann <arnd@...db.de>,
	"Mike A. Chan" <mikechan@...gle.com>,
	devicetree-discuss@...ts.ozlabs.org, linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-mmc@...r.kernel.org, csd_b@...dt.org
Subject: Re: [PATCH] ARM: mmc: bcm281xx SDHCI driver

On 05/08/2013 11:55 PM, Christian Daudt wrote:
> Add SDHCI driver for the Broadcom 281xx SoCs. Also
> add bindings for it into bcm281xx dts files.
> Still missing:
>  - power managemement

> diff --git a/drivers/mmc/host/sdhci-bcm-kona.c b/drivers/mmc/host/sdhci-bcm-kona.c

> +	/*
> +	 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
> +	 * Back-to-Back writes to same register needs delay when SD bus clock
> +	 * is very low w.r.t AHB clock, mainly during boot-time and during card
> +	 * insert-removal.
> +	 */
> +	udelay(1000);
> +	sdhci_writel(host, val, KONA_SDHOST_CORECTRL);

This sounds very similar to the workaround in
drivers/mmc/host/sdhci-bcm2835.c. Is this the same IP block supported by
that driver? Perhaps not, since bcm2835 apparently needs other WARs such
as always using 32-bit IO and hence needing custom read/write w/b
functions to do read-modify-write which isn't here?
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