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Message-Id: <1368528334-13595-3-git-send-email-prabhakar.csengg@gmail.com>
Date: Tue, 14 May 2013 16:15:31 +0530
From: Lad Prabhakar <prabhakar.csengg@...il.com>
To: LMML <linux-media@...r.kernel.org>
Cc: LKML <linux-kernel@...r.kernel.org>,
DLOS <davinci-linux-open-source@...ux.davincidsp.com>,
"Lad, Prabhakar" <prabhakar.csengg@...il.com>,
Hans Verkuil <hans.verkuil@...co.com>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Mauro Carvalho Chehab <mchehab@...hat.com>,
Guennadi Liakhovetski <g.liakhovetski@....de>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Sakari Ailus <sakari.ailus@....fi>
Subject: [PATCH 2/5] media: i2c: tvp7002: rearrange description of structure members
From: Lad, Prabhakar <prabhakar.csengg@...il.com>
This patch rearranges the description of field members of
struct tvp7002_config. Also as the all the fields where accepting
a value either 0/1, made the members as bool.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@...il.com>
Cc: Hans Verkuil <hans.verkuil@...co.com>
Cc: Laurent Pinchart <laurent.pinchart@...asonboard.com>
Cc: Mauro Carvalho Chehab <mchehab@...hat.com>
Cc: Guennadi Liakhovetski <g.liakhovetski@....de>
Cc: Sylwester Nawrocki <s.nawrocki@...sung.com>
Cc: Sakari Ailus <sakari.ailus@....fi>
Cc: linux-kernel@...r.kernel.org
Cc: davinci-linux-open-source@...ux.davincidsp.com
---
include/media/tvp7002.h | 44 ++++++++++++++++++++------------------------
1 files changed, 20 insertions(+), 24 deletions(-)
diff --git a/include/media/tvp7002.h b/include/media/tvp7002.h
index 7123048..fadb6af 100644
--- a/include/media/tvp7002.h
+++ b/include/media/tvp7002.h
@@ -28,31 +28,27 @@
#define TVP7002_MODULE_NAME "tvp7002"
-/* Platform-dependent data
- *
- * clk_polarity:
- * 0 -> data clocked out on rising edge of DATACLK signal
- * 1 -> data clocked out on falling edge of DATACLK signal
- * hs_polarity:
- * 0 -> active low HSYNC output
- * 1 -> active high HSYNC output
- * sog_polarity:
- * 0 -> normal operation
- * 1 -> operation with polarity inverted
- * vs_polarity:
- * 0 -> active low VSYNC output
- * 1 -> active high VSYNC output
- * fid_polarity:
- * 0 -> the field ID output is set to logic 1 for an odd
- * field (field 1) and set to logic 0 for an even
- * field (field 0).
- * 1 -> operation with polarity inverted.
+/**
+ * struct tvp7002_config - Platform dependent data
+ *@..._polarity: Clock polarity
+ * 0 - Data clocked out on rising edge of DATACLK signal
+ * 1 - Data clocked out on falling edge of DATACLK signal
+ *@...polarity: HSYNC polarity
+ * 0 - Active low HSYNC output, 1 - Active high HSYNC output
+ *@...polarity: VSYNC Polarity
+ * 0 - Active low VSYNC output, 1 - Active high VSYNC output
+ *@..._polarity: Active-high Field ID polarity.
+ * 0 - The field ID output is set to logic 1 for an odd field
+ * (field 1) and set to logic 0 for an even field (field 0).
+ * 1 - Operation with polarity inverted.
+ *@..._polarity: Active high Sync on Green output polarity.
+ * 0 - Normal operation, 1 - Operation with polarity inverted
*/
struct tvp7002_config {
- u8 clk_polarity;
- u8 hs_polarity;
- u8 vs_polarity;
- u8 fid_polarity;
- u8 sog_polarity;
+ bool clk_polarity;
+ bool hs_polarity;
+ bool vs_polarity;
+ bool fid_polarity;
+ bool sog_polarity;
};
#endif
--
1.7.4.1
--
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