linux-kernel - Re: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20130514225054.GI18614@n2100.arm.linux.org.uk>
Date:	Tue, 14 May 2013 23:50:54 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Stephen Warren <swarren@...dotorg.org>
Cc:	Jongsung Kim <neidhard.kim@....com>,
	'Greg Kroah-Hartman' <gregkh@...uxfoundation.org>,
	jslaby@...e.cz, linux-serial@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-rpi-kernel@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] ARM: PL011: add support for extended FIFO-size of
	PL011-r1p5

On Tue, May 14, 2013 at 03:03:14PM -0600, Stephen Warren wrote:
> On 05/14/2013 01:15 AM, Jongsung Kim wrote:
> > Stephen Warren <swarren@...dotorg.org> :
> >> For reference, the AMBA periphid of the UART device there is 0x00341011.
> >> The nibble "3" is the revision being tested in:
> > 
> > The UART device has periphid 0x00341011, and is compatible with the
> > original PL011 prior to r1p5. Not with r1p5. It could be a possible
> > way to specify the compatible periphid (such as 0x00241011) instead
> > of just 0x0 when initializing the amba_device for the UART.
> > 
> >>> +static unsigned int get_fifosize_arm(unsigned int periphid)
> >>> +{
> >>> +	unsigned int rev = (periphid >> 20) & 0xf;
> >>> +	return rev < 3 ? 16 : 32;
> >>> +}
> ...
> > Doesn't the BCM2835 UART have anything different from the ARM PL011?
> > What about the UARTPCellID registers? They are set to 0xb105f00d with
> > the ARM PL011.
> 
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation
> for the BCM2835 chip), I see:
> 
> =====
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =====
> 
> That seems to imply that not all r1p5 PL011s actually have a depth-32
> FIFO. Perhaps this is a configurable property of the IP block, not
> something that all r1p5 have?
> 
> I can't check the UARTPCellID registers right now.

The PCellID value is a marker for primecells, and is common to all primecells
which implement the ID scheme.  It's the other ID registers you want. :)
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/