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Message-ID: <CACRpkdaGBjUfhfT2zCEeNmMh3KhouOMjKSB7H6_cu_uDM6cm=w@mail.gmail.com>
Date: Fri, 17 May 2013 14:20:49 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Heiko Stübner <heiko@...ech.de>
Cc: Dan Williams <djbw@...com>, Vinod Koul <vinod.koul@...el.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
linux-samsung-soc <linux-samsung-soc@...r.kernel.org>,
Kukjin Kim <kgene.kim@...sung.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Russell King - ARM Linux <linux@....linux.org.uk>
Subject: Re: [RFC 2/4] dma: add dmaengine driver for Samsung s3c24xx SoCs
On Wed, May 15, 2013 at 10:31 PM, Heiko Stübner <heiko@...ech.de> wrote:
> If I understand the writel semantics and the thread from you from 2011 [0]
> correctly, only the writel to DMASKTRIG mustn't be relaxed to make sure the
> settings registers are written to before, so like:
>
> writel_relaxed(txd->src_addr, phy->base + DISRC);
> writel_relaxed(txd->disrcc, phy->base + DISRCC);
> writel_relaxed(txd->dst_addr, phy->base + DIDST);
> writel_relaxed(txd->didstc, phy->base + DIDSTC);
> writel_relaxed(dcon, phy->base + DCON);
>
> val = readl_relaxed(phy->base + DMASKTRIG);
> val &= ~DMASKTRIG_STOP;
> val |= DMASKTRIG_ON;
> writel(val, phy->base + DMASKTRIG);
Yep. That will drain write buffers etc and make sure all outstanding writes hit
the hardware.
Yours,
Linus Walleij
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