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Message-Id: <1369116149-2361-1-git-send-email-neidhard.kim@lge.com>
Date: Tue, 21 May 2013 15:02:29 +0900
From: Jongsung Kim <neidhard.kim@....com>
To: swarren@...dotorg.org, linux@....linux.org.uk,
gregkh@...uxfoundation.org, jslaby@...e.cz
Cc: linux-serial@...r.kernel.org, linux-rpi-kernel@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Jongsung Kim <neidhard.kim@....com>
Subject: [PATCH] ARM: bcm2835: override the HW UART periphid
Stephen Warren reported the recent commit 78506f2 (add support for
extended FIFO-size of PL011-r1p5) breaks the serial port on the
BCM2835 ARM SoC.
A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs.
The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep
FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for
this compatibility issue, this patch overrides the HW UART periphid
register values with the actually compatible UART periphid 0x00241011
(r1p3 or r1p4).
Reported-by: Stephen Warren <swarren@...dotorg.org>
Signed-off-by: Jongsung Kim <neidhard.kim@....com>
---
arch/arm/boot/dts/bcm2835.dtsi | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index f0052dc..1e12aef 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -44,6 +44,7 @@
reg = <0x7e201000 0x1000>;
interrupts = <2 25>;
clock-frequency = <3000000>;
+ arm,primecell-periphid = <0x00241011>;
};
gpio: gpio {
--
1.7.1
--
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