linux-kernel - [tip:irq/core] genirq: Generic chip: Handle separate mask registers

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Message-ID: <tip-af80b0fed67261dcba2ce2406db1d553d07cbe75@git.kernel.org>
Date:	Wed, 29 May 2013 02:17:16 -0700
From:	tip-bot for Gerlando Falauto <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	mingo@...nel.org, moinejf@...e.fr, jgunthorpe@...idianresearch.com,
	arnd@...db.de, Holger.Brunck@...mile.com,
	thomas.petazzoni@...e-electrons.com, kernel@...tstofly.org,
	linux@....linux.org.uk, simon@...uanux.org,
	ezequiel.garcia@...e-electrons.com, tglx@...utronix.de,
	joravec@...wtech.com, maxime.ripard@...e-electrons.com,
	rob@...dley.net, nico@...xnic.net, linux-kernel@...r.kernel.org,
	ben-linux@...ff.org, hpa@...or.com, grant.likely@...aro.org,
	jason@...edaemon.net, gerlando.falauto@...mile.com,
	gregory.clement@...e-electrons.com,
	sebastian.hesselbarth@...il.com, rob.herring@...xeda.com,
	andrew@...n.ch
Subject: [tip:irq/core] genirq: Generic chip:
  Handle separate mask registers

Commit-ID:  af80b0fed67261dcba2ce2406db1d553d07cbe75
Gitweb:     http://git.kernel.org/tip/af80b0fed67261dcba2ce2406db1d553d07cbe75
Author:     Gerlando Falauto <gerlando.falauto@...mile.com>
AuthorDate: Mon, 6 May 2013 14:30:21 +0000
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Wed, 29 May 2013 10:57:10 +0200

genirq: Generic chip: Handle separate mask registers

There are cases where all irq_chip_type instances have separate mask
registers, making a shared mask register cache unsuitable for the
purpose.

Introduce a new flag IRQ_GC_MASK_CACHE_PER_TYPE. If set, point the per
chip mask pointer to the per chip private mask cache instead.

[ tglx: Simplified code, renamed flag and massaged changelog ]

Signed-off-by: Gerlando Falauto <gerlando.falauto@...mile.com>
Cc: Andrew Lunn <andrew@...n.ch>
Cc: Joey Oravec <joravec@...wtech.com>
Cc: Lennert Buytenhek <kernel@...tstofly.org>
Cc: Russell King - ARM Linux <linux@....linux.org.uk>
Cc: Jason Gunthorpe <jgunthorpe@...idianresearch.com>
Cc: Holger Brunck <Holger.Brunck@...mile.com>
Cc: Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>
Acked-by: Grant Likely <grant.likely@...aro.org>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Cc: Jason Cooper <jason@...edaemon.net>
Cc: Arnd Bergmann <arnd@...db.de>
Cc: devicetree-discuss@...ts.ozlabs.org
Cc: Rob Herring <rob.herring@...xeda.com>
Cc: Ben Dooks <ben-linux@...ff.org>
Cc: Gregory Clement <gregory.clement@...e-electrons.com>
Cc: Simon Guinot <simon@...uanux.org>
Cc: linux-arm-kernel@...ts.infradead.org
Cc: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
Cc: Jean-Francois Moine <moinejf@...e.fr>
Cc: Nicolas Pitre <nico@...xnic.net>
Cc: Rob Landley <rob@...dley.net>
Cc: Maxime Ripard <maxime.ripard@...e-electrons.com>
Link: http://lkml.kernel.org/r/20130506142539.152569748@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 include/linux/irq.h       |  2 ++
 kernel/irq/generic-chip.c | 17 ++++++++++-------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 38709a3..7f1f015 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -704,10 +704,12 @@ struct irq_chip_generic {
  * @IRQ_GC_INIT_NESTED_LOCK:	Set the lock class of the irqs to nested for
  *				irq chips which need to call irq_set_wake() on
  *				the parent irq. Usually GPIO implementations
+ * @IRQ_GC_MASK_CACHE_PER_TYPE:	Mask cache is chip type private
  */
 enum irq_gc_flags {
 	IRQ_GC_INIT_MASK_CACHE		= 1 << 0,
 	IRQ_GC_INIT_NESTED_LOCK		= 1 << 1,
+	IRQ_GC_MASK_CACHE_PER_TYPE	= 1 << 2,
 };
 
 /* Generic chip callback functions */
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index 113d9eb..da2a941 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -241,18 +241,21 @@ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
 {
 	struct irq_chip_type *ct = gc->chip_types;
 	unsigned int i;
+	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
 
 	raw_spin_lock(&gc_lock);
 	list_add_tail(&gc->list, &gc_list);
 	raw_spin_unlock(&gc_lock);
 
-	/* Init mask cache ? */
-	if (flags & IRQ_GC_INIT_MASK_CACHE)
-		gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
-
-	/* Initialize mask cache pointer */
-	for (i = 0; i < gc->num_ct; i++)
-		ct[i].mask_cache = &gc->mask_cache;
+	for (i = 0; i < gc->num_ct; i++) {
+		if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
+			mskptr = &ct[i].mask_cache_priv;
+			mskreg = ct[i].regs.mask;
+		}
+		ct[i].mask_cache = mskptr;
+		if (flags & IRQ_GC_INIT_MASK_CACHE)
+			*mskptr = irq_reg_readl(gc->reg_base + mskreg);
+	}
 
 	for (i = gc->irq_base; msk; msk >>= 1, i++) {
 		if (!(msk & 0x01))
--
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