linux-kernel - Re: [RFC PATCHv4 6/6] irqchip: TI-Nspire irqchip support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 30 May 2013 22:29:45 +0100
From:	Grant Likely <grant.likely@...retlab.ca>
To:	Daniel Tang <dt.tangr@...il.com>,
	linux-arm-kernel@...ts.infradead.org,
	"linux@....linux.org.uk ARM Linux" <linux@....linux.org.uk>
Cc:	Daniel Tang <dt.tangr@...il.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	Arnd Bergmann <arnd@...db.de>,
	"fabian@...ter-vogt.de Vogt" <fabian@...ter-vogt.de>,
	Lionel Debroux <lionel_debroux@...oo.fr>,
	linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [RFC PATCHv4 6/6] irqchip: TI-Nspire irqchip support

On Sat, 25 May 2013 21:08:07 +1000, Daniel Tang <dt.tangr@...il.com> wrote:
> Add support for the interrupt controller on TI-Nspires.
> 
> Signed-off-by: Daniel Tang <dt.tangr@...il.com>
[...]
> +static void nspire_irq_ack(struct irq_data *irqd)
> +{
> +	void __iomem *base = irq_io_base;
> +
> +	if (irqd->hwirq < FIQ_START)
> +		base += IO_IRQ_BASE;
> +	else
> +		base += IO_FIQ_BASE;
> +
> +	readl(base + IO_RESET);
> +}
> +
> +static void nspire_irq_unmask(struct irq_data *irqd)
> +{
> +	void __iomem *base = irq_io_base;
> +	int irqnr = irqd->hwirq;
> +
> +	if (irqnr < FIQ_START) {
> +		base += IO_IRQ_BASE;
> +	} else {
> +		irqnr -= MAX_INTRS;
> +		base += IO_FIQ_BASE;
> +	}
> +
> +	writel((1<<irqnr), base + IO_ENABLE);
> +}
> +
> +static void nspire_irq_mask(struct irq_data *irqd)
> +{
> +	void __iomem *base = irq_io_base;
> +	int irqnr = irqd->hwirq;
> +
> +	if (irqnr < FIQ_START) {
> +		base += IO_IRQ_BASE;
> +	} else {
> +		irqnr -= FIQ_START;
> +		base += IO_FIQ_BASE;
> +	}
> +
> +	writel((1<<irqnr), base + IO_DISABLE);
> +}
> +
> +static struct irq_chip nspire_irq_chip = {
> +	.name		= "nspire_irq",
> +	.irq_ack	= nspire_irq_ack,
> +	.irq_mask	= nspire_irq_mask,
> +	.irq_unmask	= nspire_irq_unmask,
> +};

Should be using irq_generic_chip here. There is no need to reimplement
the above ack, mask and unmask functions. You should find the
irq_alloc_domain_generic_chips() patch in the tip tree irq/for-arm
branch. That branch is staged for merging in v3.11

Otherwise the patch looks good.

g.

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/