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Message-ID: <20130531192528.21525.46053@quantum>
Date: Fri, 31 May 2013 12:25:28 -0700
From: Mike Turquette <mturquette@...aro.org>
To: Alexandre Courbot <acourbot@...dia.com>,
Stephen Warren <swarren@...dotorg.org>,
Peter De Schrijver <pdeschrijver@...dia.com>
Cc: linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
gnurou@...il.com, Alexandre Courbot <acourbot@...dia.com>
Subject: Re: [PATCH RESEND] ARM: tegra114: correctly output clk_32k
Quoting Alexandre Courbot (2013-05-25 19:56:31)
> Tegra has a blink timer register that allows to modulate the
> clk_32k clock before outputting it. Since clk_32k is presented to the
> kernel as a fixed clock, make sure this register does not tamper with
> the clock frequency and that clk_32k is outputted as-is, similarly to
> what is done on t20 and t30.
>
> Signed-off-by: Alexandre Courbot <acourbot@...dia.com>
> Acked-by: Stephen Warren <swarren@...dia.com>
Taken into clk-next.
Regards,
Mike
> ---
> drivers/clk/tegra/clk-tegra114.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index d78e16e..dc76d67 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -127,6 +127,7 @@
> #define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
> #define PMC_CTRL 0
> #define PMC_CTRL_BLINK_ENB 7
> +#define PMC_BLINK_TIMER 0x40
>
> #define OSC_CTRL 0x50
> #define OSC_CTRL_OSC_FREQ_SHIFT 28
> @@ -1625,6 +1626,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
> clks[clk_out_3] = clk;
>
> /* blink */
> + /* clear the blink timer register to directly output clk_32k */
> + writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
> clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
> pmc_base + PMC_DPD_PADS_ORIDE,
> PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
> --
> 1.8.2.3
--
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