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Message-ID: <CACxGe6se9rqOdLAqj7XQ+Awa5HP+2k1t7pN1AYOAPdiL2o3AjQ@mail.gmail.com>
Date: Mon, 3 Jun 2013 10:51:06 +0100
From: Grant Likely <grant.likely@...retlab.ca>
To: Vineet Gupta <Vineet.Gupta1@...opsys.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Christian Ruppert <christian.ruppert@...lis.com>,
Rob Herring <rob.herring@...xeda.com>,
Rob Landley <rob@...dley.net>,
devicetree-discuss <devicetree-discuss@...ts.ozlabs.org>,
"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Pierrick Hascoet <pierrick.hascoet@...lis.com>
Subject: Re: [PATCH V3] irqchip: Add TB10x interrupt controller driver
On Mon, Jun 3, 2013 at 5:05 AM, Vineet Gupta <Vineet.Gupta1@...opsys.com> wrote:
> On 06/01/2013 03:48 AM, Grant Likely wrote:
>> If I were working on this system I'd drop the
>> snps,arc700-intc node entirely and have a single abilis,tb10x-intc that
>> encapsulated the properties of both (you would of course want to share
>> handler functions for the 'normal' inputs without the custom features).
>> That would eliminate the goofyness of listing 27 separate interrupts in
>> the abilis,tb10x-ictl interrupts property.
>
> But how is this different from other systems with a primary in-core intc and a
> cascaded external intc. How do they do it. I guess I need to read up more on this.
Usually cascaded irq controllers have multiple irqs multiplexed onto a
single irq on the parent controller. It's the 1:1 situation that makes
this controller odd.
g,
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