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Message-ID: <1370440301-3562-1-git-send-email-pdeschrijver@nvidia.com>
Date: Wed, 5 Jun 2013 16:51:24 +0300
From: Peter De Schrijver <pdeschrijver@...dia.com>
To: Peter De Schrijver <pdeschrijver@...dia.com>
CC: <linux-arm-kernel@...ts.infradead.org>, <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Thierry Reding <thierry.reding@...il.com>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH 0/2] PLL m,n,p init from SoC files
The m,n,p fields don't have the same bit offset and width across all PLLs.
This patchset allows SoC specific files to indicate the offset and width.
It also provides the data for Tegra114.
Peter De Schrijver (2):
clk: tegra: allow PLL m,n,p init from SoC files
clk: tegra: PLL m,n,p init for Tegra114
drivers/clk/tegra/clk-pll.c | 60 ++++++++++++++++-------------
drivers/clk/tegra/clk-tegra114.c | 77 ++++++++++++++++++++++++++++++++++++++
drivers/clk/tegra/clk.h | 32 ++++++++++------
3 files changed, 130 insertions(+), 39 deletions(-)
--
1.7.7.rc0.72.g4b5ea.dirty
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