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Message-ID: <20130605135445.GP3847@tbergstrom-lnx.Nvidia.com>
Date: Wed, 5 Jun 2013 16:54:45 +0300
From: Peter De Schrijver <pdeschrijver@...dia.com>
To: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"mturquette@...aro.org" <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Thierry Reding <thierry.reding@...il.com>,
"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/2] PLL m,n,p init from SoC files
On Wed, Jun 05, 2013 at 03:51:24PM +0200, Peter De Schrijver wrote:
> The m,n,p fields don't have the same bit offset and width across all PLLs.
> This patchset allows SoC specific files to indicate the offset and width.
> It also provides the data for Tegra114.
>
Depends on 'clk: tegra: pllc and pllxc should use pdiv_map'
Cheers,
Peter.
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