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Message-ID: <20130611142324.GD29135@zurbaran>
Date: Tue, 11 Jun 2013 16:23:24 +0200
From: Samuel Ortiz <sameo@...ux.intel.com>
To: Sebastian Andrzej Siewior <bigeasy@...utronix.de>
Cc: Lee Jones <lee.jones@...aro.org>,
BenoƮt Cousson <b-cousson@...com>,
Tony Lindgren <tony@...mide.com>,
Jonathan Cameron <jic23@....ac.uk>,
Dmitry Torokhov <dmitry.torokhov@...il.com>,
Felipe Balbi <balbi@...com>, linux-kernel@...r.kernel.org,
linux-omap@...r.kernel.org, linux-iio@...r.kernel.org,
linux-input@...r.kernel.org, "Patil, Rachna" <rachna@...com>
Subject: Re: [PATCH 04/22] input/ti_am33x_tsc: Order of TSC wires, made
configurable
Hi Sebastian,
On Tue, Jun 11, 2013 at 01:30:50PM +0200, Sebastian Andrzej Siewior wrote:
> diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
> index eeead15..2d78af8 100644
> --- a/include/linux/mfd/ti_am335x_tscadc.h
> +++ b/include/linux/mfd/ti_am335x_tscadc.h
> @@ -71,8 +71,6 @@
> #define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
> #define STEPCONFIG_INP_MASK (0xF << 19)
> #define STEPCONFIG_INP(val) ((val) << 19)
> -#define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2)
> -#define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3)
> #define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
> #define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
> #define STEPCONFIG_FIFO1 BIT(26)
> @@ -94,7 +92,6 @@
> #define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
> #define STEPCHARGE_INP_MASK (0xF << 19)
> #define STEPCHARGE_INP(val) ((val) << 19)
> -#define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1)
> #define STEPCHARGE_RFM_MASK (3 << 23)
> #define STEPCHARGE_RFM(val) ((val) << 23)
> #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
> @@ -116,6 +113,13 @@
> #define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
> #define CNTRLREG_TSCENB BIT(7)
>
> +#define XPP STEPCONFIG_XPP
> +#define XNP STEPCONFIG_XNP
> +#define XNN STEPCONFIG_XNN
> +#define YPP STEPCONFIG_YPP
> +#define YPN STEPCONFIG_YPN
> +#define YNN STEPCONFIG_YNN
What is that for ? Isn't STEPCONFIG_XPP explicit enough ?
Cheers,
Samuel.
--
Intel Open Source Technology Centre
http://oss.intel.com/
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