lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20130612002623.8816.29653@quantum>
Date:	Tue, 11 Jun 2013 17:26:23 -0700
From:	Mike Turquette <mturquette@...aro.org>
To:	Peter De Schrijver <pdeschrijver@...dia.com>,
	Peter De Schrijver <pdeschrijver@...dia.com>
Cc:	<linux-arm-kernel@...ts.infradead.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Prashant Gaikwad <pgaikwad@...dia.com>,
	<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: tegra: pllp_out2 divider is int only

Quoting Peter De Schrijver (2013-06-05 06:37:17)
> The pllp_out2 should be integer only, the fractional bit should always be 0.
> 
> Signed-off-by: Peter De Schrijver <pdeschrijver@...dia.com>

Taken into clk-next.

Thanks,
Mike

> ---
>  drivers/clk/tegra/clk-tegra114.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index eb27764..5e029fe 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1203,8 +1203,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
>         /* PLLP_OUT2 */
>         clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
>                                 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
> -                               TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
> -                               &pll_div_lock);
> +                               TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
> +                               8, 1, &pll_div_lock);
>         clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
>                                 clk_base + PLLP_OUTA, 17, 16,
>                                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
> -- 
> 1.7.7.rc0.72.g4b5ea.dirty
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ