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Message-ID: <20130619084542.GB3847@tbergstrom-lnx.Nvidia.com>
Date: Wed, 19 Jun 2013 11:45:42 +0300
From: Peter De Schrijver <pdeschrijver@...dia.com>
To: Paul Walmsley <pwalmsley@...dia.com>
CC: "linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
"mturquette@...aro.org" <mturquette@...aro.org>,
Aleksandr Frid <afrid@...dia.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control
On Fri, Jun 07, 2013 at 02:19:09PM +0200, Paul Walmsley wrote:
> Add DFLL DVCO reset line control functions to the CAR IP block driver.
>
> The DVCO present in the DFLL IP block has a separate reset line,
> exposed via the CAR IP block. This reset line is asserted upon SoC
> reset. Unless something (such as the DFLL driver) deasserts this
> line, the DVCO will not oscillate, although reads and writes to the
> DFLL IP block will complete.
>
> Thanks to Aleksandr Frid <afrid@...dia.com> for identifying this and
> saving hours of debugging time.
>
> Signed-off-by: Paul Walmsley <pwalmsley@...dia.com>
> Cc: Aleksandr Frid <afrid@...dia.com>
> Cc: Peter De Schrijver <pdeschrijver@...dia.com>
Reviewed-by: <pdeschrijver@...dia.com>
Cheers,
Peter.
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