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Message-Id: <1371933764-24875-7-git-send-email-tomasz.figa@gmail.com>
Date: Sat, 22 Jun 2013 22:42:38 +0200
From: Tomasz Figa <tomasz.figa@...il.com>
To: linux-samsung-soc@...r.kernel.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-spi@...r.kernel.org, alsa-devel@...a-project.org,
Kukjin Kim <kgene.kim@...sung.com>,
Vinod Koul <vinod.koul@...el.com>, Dan Williams <djbw@...com>,
Linus Walleij <linus.walleij@...aro.org>,
Alessandro Rubini <rubini@...dd.com>,
Giancarlo Asnaghi <giancarlo.asnaghi@...com>,
Mark Brown <broonie@...nel.org>,
Grant Likely <grant.likely@...aro.org>,
Sangbeom Kim <sbkim73@...sung.com>,
Liam Girdwood <lgirdwood@...il.com>,
Jaroslav Kysela <perex@...ex.cz>, Takashi Iwai <tiwai@...e.de>,
Padmavathi Venna <padma.v@...sung.com>,
Thomas Abraham <thomas.abraham@...aro.org>,
Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
Heiko Stübner <heiko@...ech.de>,
Sylwester Nawrocki <sylvester.nawrocki@...il.com>,
Russell King - ARM Linux <linux@....linux.org.uk>,
Alban Bedel <alban.bedel@...onic-design.de>,
Tomasz Figa <tomasz.figa@...il.com>
Subject: [RFC PATCH v2 06/12] dmaengine: PL08x: Fix reading the byte count in cctl
From: Alban Bedel <alban.bedel@...onic-design.de>
There are more fields than just SWIDTH in CH_CONTROL register, so read
register value must be masked in addition to shifting.
Signed-off-by: Alban Bedel <alban.bedel@...onic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@...il.com>
---
drivers/dma/amba-pl08x.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 89b8120..1eeb911 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -469,6 +469,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
/* The source width defines the number of bytes */
u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
+ cctl &= PL080_CONTROL_SWIDTH_MASK;
+
switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
case PL080_WIDTH_8BIT:
break;
@@ -487,6 +489,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
/* The source width defines the number of bytes */
u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
+ cctl &= PL080_CONTROL_SWIDTH_MASK;
+
switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
case PL080_WIDTH_8BIT:
break;
--
1.8.2.1
--
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