linux-kernel - Re: MTRR use in drivers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <43cfe710-f22c-4b0b-b7e0-a3c8e6a49096@email.android.com>
Date:	Sun, 23 Jun 2013 17:31:23 -0700
From:	"H. Peter Anvin" <hpa@...or.com>
To:	Henrique de Moraes Holschuh <hmh@....eng.br>
CC:	Brice Goglin <brice.goglin@...il.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	David Airlie <airlied@...ux.ie>,
	dri-devel@...ts.freedesktop.org
Subject: Re: MTRR use in drivers

The aliasing doesn't matter for Linux because we map the high and low half the same.

Henrique de Moraes Holschuh <hmh@....eng.br> wrote:

>On Sun, 23 Jun 2013, H. Peter Anvin wrote:
>> On 06/23/2013 02:56 PM, Henrique de Moraes Holschuh wrote:
>> > 
>> > And as far as I could find from Intel's not-that-complete public
>> > "specification updates", we are applying the errata workaround to a
>few more
>> > processors than strictly required, but since I have no idea how to
>write a
>> > test case, I can't whitelist the 3rd-gen Pentium M on my T43, nor
>can I get
>> > ThinkPad owners to test it for us on 1st and 2nd-gen Pentium M and
>report
>> > back.
>> 
>> Which specific erratum are you referring to, here?  The "WC becomes
>UC"
>> erratum?  I don't think there is a sane testcase for it since it
>needs a
>> very complicated setup to trigger.
>
>There are at least two different nasty PAT issues that are not always
>critical, and one that outright hangs the processor (if the unsupported
>aliasing of WB with UC/WC happens).
>
>Interestingly enough, most of the P4-Xeons and P4 do not appear to have
>the
>"WC becomes UC" errata.
>
>However, LOTS of P4, M-P4, Xeon PIII, Xeon, and Pentium M have a bug
>where
>the four highest entries in the PAT table are inactive (aliased to the
>four
>lowest entries) in mode B (PSE) and mode C (PAE) for 4k pages.  They
>work
>fine for large pages.
>
>Also, lots of them can hang if you ever alias WB with UC or WC (which
>is
>apparently an unsupported configuration anyway, or so it says in the
>errata).
>
>There are other weird aliasing nasties, such as one where you get
>memory
>corruption if you alias WB data with code (being accessed as UC or WC)
>in
>the same cacheline, and some stuff such as weirdness should the page
>table
>be on WC memory...
>
>I can track down most of the CPUIDs involved if you want, but someone
>from
>Intel would be better (I assume they actually have access to the errata
>documentation in some less idiotic way than reading a ton of badly
>indexed
>PDFs that take forever to find in their site).

-- 
Sent from my mobile phone. Please excuse brevity and lack of formatting.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/