linux-kernel - linux-next: manual merge of the clk tree with the samsung tree

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Message-Id: <20130624154828.292bd8800c80c526695c1659@canb.auug.org.au>
Date:	Mon, 24 Jun 2013 15:48:28 +1000
From:	Stephen Rothwell <sfr@...b.auug.org.au>
To:	Mike Turquette <mturquette@...aro.org>
Cc:	linux-next@...r.kernel.org, linux-kernel@...r.kernel.org,
	Tushar Behera <tushar.behera@...aro.org>,
	Sachin Kamat <sachin.kamat@...aro.org>,
	Kukjin Kim <kgene.kim@...sung.com>
Subject: linux-next: manual merge of the clk tree with the samsung tree

Hi Mike,

Today's linux-next merge of the clk tree got a conflict in
drivers/clk/samsung/clk-exynos4.c between commit 6082f908b060 ("clk:
exynos4: Staticize local symbols") from the samsung tree and commit
82ba93b27cf5 ("clk: exynos4: Fix clock aliases for cpufreq related
clocks") from the clk tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@...b.auug.org.au

diff --cc drivers/clk/samsung/clk-exynos4.c
index 50af410,94c5e1a..0000000
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@@ -355,9 -355,9 +355,9 @@@ static struct samsung_fixed_rate_clock 
  };
  
  /* list of mux clocks supported in all exynos4 soc's */
 -struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
 +static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
- 	MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
- 			CLK_SET_RATE_PARENT, 0),
+ 	MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ 			CLK_SET_RATE_PARENT, 0, "mout_apll"),
  	MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
  	MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
  	MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
@@@ -423,9 -423,9 +423,9 @@@ static struct samsung_mux_clock exynos4
  };
  
  /* list of mux clocks supported in exynos4x12 soc */
 -struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
 +static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
- 	MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
- 			SRC_CPU, 24, 1),
+ 	MUX_A(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
+ 			SRC_CPU, 24, 1, "mout_mpll"),
  	MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
  	MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
  	MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,

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