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Date:	Mon, 24 Jun 2013 15:08:28 -0700
From:	Stephen Boyd <sboyd@...eaurora.org>
To:	Srinivas KANDAGATLA <srinivas.kandagatla@...com>
CC:	John Stultz <john.stultz@...aro.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Grant Likely <grant.likely@...aro.org>,
	Rob Herring <rob.herring@...xeda.com>,
	Rob Landley <rob@...dley.net>,
	devicetree-discuss@...ts.ozlabs.org, linux-doc@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Linus Walleij <linus.walleij@...aro.org>,
	Stuart Menefy <stuart.menefy@...com>,
	Arnd Bergmann <arnd@...db.de>,
	Rob Herring <robherring2@...il.com>,
	Will Deacon <will.deacon@....com>
Subject: Re: [PATCH v5] clocksource:arm_global_timer: Add ARM global timer
 support.

On 06/24/13 08:53, Srinivas KANDAGATLA wrote:
> +#include <linux/clkdev.h>

Why do you need this include?

> +#include <asm/mach/irq.h>

And this one?

> +static u64 gt_counter_read(void)
> +{
> +	u64 counter;
> +	u32 lower;
> +	u32 upper, old_upper;
> +
> +	upper = readl_relaxed(gt_base + GT_COUNTER1);
> +	do {
> +		old_upper = upper;
> +		lower = readl_relaxed(gt_base + GT_COUNTER0);
> +		upper = readl_relaxed(gt_base + GT_COUNTER1);
[snip]
> +static void gt_compare_set(unsigned long delta, int periodic)
> +{
> +	u64 counter = gt_counter_read();
> +	unsigned long ctrl = readl(gt_base + GT_CONTROL);
> +
> +	counter += delta;
> +	ctrl &=  ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE);
> +
> +	writel(ctrl, gt_base + GT_CONTROL);
> +	writel(lower_32_bits(counter), gt_base + GT_COMP0);
> +	writel(upper_32_bits(counter), gt_base + GT_COMP1);
> +
> +	if (periodic) {
> +		writel(delta, gt_base + GT_AUTO_INC);
> +		ctrl |= GT_CONTROL_AUTO_INC;
> +	}
> +
> +	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
> +	writel(ctrl, gt_base + GT_CONTROL);
> +}

Why is there a mix of the relaxed and non-relaxed io accessors?

> +#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
> +static u32 gt_sched_clock_read(void)

notrace

> +{
> +	if (!gt_base)
> +		return 0;

Seems impossible? Remove this check?

-- 
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