linux-kernel - Re: [PATCH 2/2] Make non-linear GPIO ranges accesible from gpiolib

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Message-ID: <CACRpkdbnXmJnPd6akeEVuU9dwAe+FOvm6boDt8=zjG_D3ZLTGg@mail.gmail.com>
Date:	Tue, 25 Jun 2013 16:27:37 +0200
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Stephen Warren <swarren@...dotorg.org>
Cc:	Christian Ruppert <christian.ruppert@...lis.com>,
	Patrice CHOTARD <patrice.chotard@...com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Grant Likely <grant.likely@...retlab.ca>,
	Rob Herring <rob.herring@...xeda.com>,
	Rob Landley <rob@...dley.net>,
	Sascha Leuenberger <sascha.leuenberger@...lis.com>,
	Pierrick Hascoet <pierrick.hascoet@...lis.com>,
	"devicetree-discuss@...ts.ozlabs.org" 
	<devicetree-discuss@...ts.ozlabs.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
	Alexandre Courbot <acourbot@...dia.com>
Subject: Re: [PATCH 2/2] Make non-linear GPIO ranges accesible from gpiolib

On Fri, Jun 21, 2013 at 11:17 PM, Stephen Warren <swarren@...dotorg.org> wrote:

> When I pushed for the concept of groups, I intended it to mean precisely
> one single thing. The points below describe this.
>
> 1) A pin is a single pin/ball/pad on the package.
>
> 2) Some register fields affect just a single pin. For example, there may
> be a register field that affects pin A8's mux setting only.
>
> 3) Some register fields affect multiple pins at once. For example,
> perhaps one register field affects both pin A8's an pin A7's mux setting
> at once.
>
> 4) Depending on HW design, all register fields might be of type
> described at (2) above, or all of the type described at (3) above, or a
> mixture of both. Tegra is a mixture.
>
> 5) I expect the concept of a pin group to solely represent the various
> groups of pins affected by each register field; in (2) above one pin per
> group, in (3) above many pins per group.
>
> Thus, to my mind, a pin group is purely a HW concept, and dictated
> purely by HW design.

This we can discuss perpetually it seems.

For Nomadik, as I've pointed out in the past it is actually:

(6): it is one register/set if bits per pin, BUT the register settings
 pertain to physical lines having electrical settings which postulate
 that they be handled in batch or wreak havoc.

I.e. it is a HW limitation in the *silicon* of *all* implementations,
but that is *not* expressed in the register map.

For the practical consequences see __nmk_config_pins if (glitch)
runpath. Handling this as a group makes perfect sense from
a hardware point of view.

Yours,
Linus Walleij
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