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Message-ID: <1606295.H1unv8GDgk@vostro.rjw.lan>
Date: Thu, 27 Jun 2013 00:44:30 +0200
From: "Rafael J. Wysocki" <rjw@...k.pl>
To: Yinghai Lu <yinghai@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Mika Westerberg <mika.westerberg@...ux.intel.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
"Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
Jesse Barnes <jbarnes@...tuousgeek.org>,
"Ronciak, John" <john.ronciak@...el.com>,
"Penner, Miles J" <miles.j.penner@...el.com>,
Bruce Allan <bruce.w.allan@...el.com>,
"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH 6/6] x86/PCI: quirk Thunderbolt PCI-to-PCI bridges
On Wednesday, June 26, 2013 03:31:18 PM Yinghai Lu wrote:
> On Wed, Jun 26, 2013 at 3:26 PM, Yinghai Lu <yinghai@...nel.org> wrote:
> > On Wed, Jun 26, 2013 at 3:18 PM, Bjorn Helgaas <bhelgaas@...gle.com> wrote:
> >> On Tue, Jun 25, 2013 at 10:22 AM, Mika Westerberg
> >> <mika.westerberg@...ux.intel.com> wrote:
> >>> Thunderbolt PCI-to-PCI bridges typically use BIOS "assisted" enumeration.
> >>> This means that the BIOS will allocate bridge resources based on some
> >>> assumptions of a maximum Thunderbolt chain. It also disables native PCIe
> >>> hotplug of the root port where the Thunderbolt host router is connected.
> >
> > We should not need tricks in this patch after
> >
> > https://patchwork.kernel.org/patch/2766521/
> >
> > [2/3] PCI / ACPI: Use boot-time resource allocation rules during hotplug
> >
>
> BTW, Rafael, looks like that "boot-time" is not accurate here.
>
> During acpi hotplug, firmare could do extra help for us like assign
> some resources to pci device bars, so it is NOT "boot-time".
Well, Linus has merged it already and besides "boot-time rules" need not
mean "boot-time resources", right?
Rafael
--
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.
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