linux-kernel - Re: [linux-sunxi] [PATCH 0/8] clocksource: sunxi: Timer fixes and cleanup

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Message-ID: <alpine.DEB.2.02.1306281211330.4013@ionos.tec.linutronix.de>
Date:	Fri, 28 Jun 2013 12:26:10 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Siarhei Siamashka <siarhei.siamashka@...il.com>
cc:	kevin <kevin@...winnertech.com>,
	"linux-sunxi@...glegroups.com" <linux-sunxi@...glegroups.com>,
	"maxime.ripard" <maxime.ripard@...e-electrons.com>,
	Hans de Goede <hdegoede@...hat.com>,
	John Stultz <john.stultz@...aro.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Emilio Lopez <emilio@...pez.com.ar>,
	孙彦邦 <sunny@...winnertech.com>,
	吴书耕 <shuge@...winnertech.com>
Subject: Re: [linux-sunxi] [PATCH 0/8] clocksource: sunxi: Timer fixes and
 cleanup

On Fri, 28 Jun 2013, Siarhei Siamashka wrote:
> On Fri, 28 Jun 2013 09:43:37 +0800
> 张猛 <kevin@...winnertech.com> wrote:
> 
> > > The A10 manual from http://free-electrons.com/~maxime/pub/datasheet/
> > > does not seem to contain any details about what bad things may happen
> > > if we try to read CNT64_LO_REG while latching is still in progress and
> > > CNT64_RL_EN bit in CNT64_CTRL_REG has not changed to zero yet.
> > > I can imagine the following possible scenarios:
> > >  1. We read either the old stale CNT64_LO_REG value or the new
> > >     correct value.
> > >  2. We read either the old stale CNT64_LO_REG value or the new
> > >     correct value, or some random garbage.
> > >  3. The processor may deadlock, eat your dog, or do some other
> > >     nasty thing.
> > >
> > > In the case of 1, we probably can get away without using any spinlocks?
> > 
> > About the 64bits counter, the latch bit is needed because of the
> > asynchronous circuit. The internal circuit of 64bits counter is
> > working under 24Mhz clock, and CNT_LO/HI is read with APB clock.
> > So the clock synchronize is needed. The function of the latch is
> > synchronous the 64bits counter from 24Mhz clock domain to APB clock
> > domain. So, if the latch is not completely, value of the CNT_LO/HI
> > maybe a random value, because some bits are latched, but others are
> > not. So, the CNT_LO/HI should be read after latch is completely.
> > The latch just takes 3 cycles of 24Mhz clock, the time is nearly
> > 0.125 micro-second.
> 
> Thanks for the clarification! It is very much appreciated.
> 
> So basically we get scenario 2, which still allows some optimizations
> compared to scenario 3. On single-core systems (Allwinner A10), it
> probably makes sense to avoid spinlocks overhead and just place

Spinlocks are NOPs on UP and just disable preemption, but they
provide you the same ordering guarantees as spinlocks on SMP. So no
special case optimization necessary.

Thanks,

	tglx