linux-kernel - Re: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during context switch

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Message-ID: <20130710175734.GZ6123@two.firstfloor.org>
Date:	Wed, 10 Jul 2013 19:57:34 +0200
From:	Andi Kleen <andi@...stfloor.org>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	Andi Kleen <andi@...stfloor.org>,
	"Yan, Zheng" <zheng.z.yan@...el.com>, linux-kernel@...r.kernel.org,
	mingo@...nel.org, eranian@...gle.com
Subject: Re: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during
 context switch

On Thu, Jul 04, 2013 at 04:00:57PM +0200, Peter Zijlstra wrote:
> On Thu, Jul 04, 2013 at 03:44:57PM +0200, Andi Kleen wrote:
> > Evidently it's not read-only on Haswell at least.
> 
> It would be ever so good if you could at least test run such patches against
> semi-current chips, not only the very latest.

So we tested some systems (old and new Atom, Westmere, Nehalem, *Bridge)
and they all have writable TOS. Also I double checked the SDM
and it actually documents these MSRs as R/W in Chapter 35

So relying on this is ok.

-Andi
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