linux-kernel - Re: [PATCH 1/2 v3] x86: introduce int3-based instruction patching

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Message-ID: <1373594948.17876.77.camel@gandalf.local.home>
Date:	Thu, 11 Jul 2013 22:09:08 -0400
From:	Steven Rostedt <rostedt@...dmis.org>
To:	Jiri Kosina <jkosina@...e.cz>
Cc:	"H. Peter Anvin" <hpa@...ux.intel.com>,
	Masami Hiramatsu <masami.hiramatsu.pt@...achi.com>,
	Jason Baron <jbaron@...mai.com>,
	Borislav Petkov <bp@...en8.de>, Joe Perches <joe@...ches.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2 v3] x86: introduce int3-based instruction patching

On Fri, 2013-07-12 at 00:31 +0200, Jiri Kosina wrote:
> On Thu, 11 Jul 2013, H. Peter Anvin wrote:
> 
> > > synchronization after replacing "all but first" instructions should not
> > > be necessary (on Intel hardware), as the syncing after the subsequent
> > > patching of the first byte provides enough safety.
> > > But there's not only Intel HW out there, and we'd rather be on a safe
> > > side.
> > 
> > Has anyone talked to AMD or VIA about this at all?  Did anyone else ever
> > make SMP-capable x86?
> 
> If Boris can verify for AMD, that'd be good; we could then just remove one 
> extra syncing of the cores as a followup (can be done any time later, both 
> for alternative.c and ftrace in fact).
> 
> With the "extra" sync, the procedure is already verified to work properly 
> by ftace.
> 

I'd like to caution on the side of safety. The extra sync really doesn't
hurt. Let's keep it in for a kernel release cycle to make sure
everything else works properly, then we can look at optimizing it.

-- Steve


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