linux-kernel - Re: [tip:x86/urgent] x86: Make sure IDT is page aligned

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Message-ID: <CAE9FiQXvfopU1SYs3OFQk8rXVgq-Hbhw6gB49u5H4O70Tx12+A@mail.gmail.com>
Date:	Sat, 13 Jul 2013 14:34:15 -0700
From:	Yinghai Lu <yinghai@...nel.org>
To:	Ingo Molnar <mingo@...nel.org>, "H. Peter Anvin" <hpa@...or.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Kees Cook <keescook@...omium.org>, pageexec@...il.com,
	Thomas Gleixner <tglx@...utronix.de>,
	"H. Peter Anvin" <hpa@...ux.intel.com>
Cc:	"linux-tip-commits@...r.kernel.org" 
	<linux-tip-commits@...r.kernel.org>
Subject: Re: [tip:x86/urgent] x86: Make sure IDT is page aligned

On Fri, Jul 12, 2013 at 8:21 PM, tip-bot for Kees Cook <tipbot@...or.com> wrote:
> Commit-ID:  c0b3450f101523a49823fa93d155f1d258e5ac6f
> Gitweb:     http://git.kernel.org/tip/c0b3450f101523a49823fa93d155f1d258e5ac6f
> Author:     Kees Cook <keescook@...omium.org>
> AuthorDate: Fri, 12 Jul 2013 15:50:17 -0700
> Committer:  H. Peter Anvin <hpa@...ux.intel.com>
> CommitDate: Fri, 12 Jul 2013 16:14:08 -0700
>
> x86: Make sure IDT is page aligned
>
> Since the IDT is referenced from a fixmap, make sure it is page aligned.
> Merge with 32-bit one, since it was already aligned to deal with F00F bug.
> This avoids the risk of it ever being moved in the bss and having the
> mapping be offset, resulting in calling incorrect handlers.

why can put idt_table not be in .bss?

>
> [ hpa: It isn't clear that this is a manifest bug in any way, but
>   tagging for -stable because it shouldn't hurt and might avoid some
>   very hard-to-debug breakages due to unrelated changes. ]
>
> Signed-off-by: Kees Cook <keescook@...omium.org>
> Link: http://lkml.kernel.org/r/20130712225017.GA5366@www.outflux.net
> Reported-by: PaX Team <pageexec@...il.com>
> Cc: stable@...r.kernel.org
> Signed-off-by: H. Peter Anvin <hpa@...ux.intel.com>
> ---
>  arch/x86/kernel/head_64.S | 4 ----
>  arch/x86/kernel/traps.c   | 7 ++-----
>  2 files changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
> index 5e4d8a8..317b8cc 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -514,10 +514,6 @@ ENTRY(phys_base)
>
>         .section .bss, "aw", @nobits
>         .align L1_CACHE_BYTES
> -ENTRY(idt_table)
> -       .skip IDT_ENTRIES * 16
> -
> -       .align L1_CACHE_BYTES
>  ENTRY(debug_idt_table)
>         .skip IDT_ENTRIES * 16
>
> diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
> index b0865e8..0952614 100644
> --- a/arch/x86/kernel/traps.c
> +++ b/arch/x86/kernel/traps.c
> @@ -68,13 +68,10 @@
>  #include <asm/setup.h>
>
>  asmlinkage int system_call(void);
> +#endif
>
> -/*
> - * The IDT has to be page-aligned to simplify the Pentium
> - * F0 0F bug workaround.
> - */
> +/* The IDT has to be page-aligned to keep it aligned with its fixmap. */
>  gate_desc idt_table[NR_VECTORS] __page_aligned_data = { { { { 0, 0 } } }, };
> -#endif

can we use put all idt_table related in to __bss.aligned section ...?

like
gate_desc idt_table[NR_VECTORS] __page_aligned_bss;

>
>  DECLARE_BITMAP(used_vectors, NR_VECTORS);
>  EXPORT_SYMBOL_GPL(used_vectors);
> --
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