linux-kernel - [tip:x86/urgent] x86, suspend: Handle CPUs which fail to #GP on RDMSR

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Date:	Mon, 15 Jul 2013 13:58:18 -0700
From:	"tip-bot for H. Peter Anvin" <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...nel.org,
	onny@...ject-insanity.org, tglx@...utronix.de, hpa@...ux.intel.com,
	rjw@...k.pl, christian.suenkenberg@...dent.kit.edu
Subject: [tip:x86/urgent] x86, suspend:
  Handle CPUs which fail to #GP on RDMSR

Commit-ID:  5ff560fd48d5b3d82fa0c3aff625c9da1a301911
Gitweb:     http://git.kernel.org/tip/5ff560fd48d5b3d82fa0c3aff625c9da1a301911
Author:     H. Peter Anvin <hpa@...ux.intel.com>
AuthorDate: Fri, 12 Jul 2013 16:48:12 -0700
Committer:  H. Peter Anvin <hpa@...ux.intel.com>
CommitDate: Mon, 15 Jul 2013 13:50:54 -0700

x86, suspend: Handle CPUs which fail to #GP on RDMSR

There are CPUs which have errata causing RDMSR of a nonexistent MSR to
not fault.  We would then try to WRMSR to restore the value of that
MSR, causing a crash.  Specifically, some Pentium M variants would
have this problem trying to save and restore the non-existent EFER,
causing a crash on resume.

Work around this by making sure we can write back the result at
suspend time.

Huge thanks to Christian Sünkenberg for finding the offending erratum
that finally deciphered the mystery.

Reported-and-tested-by: Johan Heinrich <onny@...ject-insanity.org>
Debugged-by: Christian Sünkenberg <christian.suenkenberg@...dent.kit.edu>
Acked-by: Rafael J. Wysocki <rjw@...k.pl>
Link: http://lkml.kernel.org/r/51DDC972.3010005@student.kit.edu
Cc: <stable@...r.kernel.org> # v3.7+
---
 arch/x86/kernel/acpi/sleep.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 2a34aaf..3312010 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -48,9 +48,20 @@ int x86_acpi_suspend_lowlevel(void)
 #ifndef CONFIG_64BIT
 	native_store_gdt((struct desc_ptr *)&header->pmode_gdt);
 
+	/*
+	 * We have to check that we can write back the value, and not
+	 * just read it.  At least on 90 nm Pentium M (Family 6, Model
+	 * 13), reading an invalid MSR is not guaranteed to trap, see
+	 * Erratum X4 in "Intel Pentium M Processor on 90 nm Process
+	 * with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90
+	 * nm process with 512-KB L2 Cache Specification Update".
+	 */
 	if (!rdmsr_safe(MSR_EFER,
 			&header->pmode_efer_low,
-			&header->pmode_efer_high))
+			&header->pmode_efer_high) &&
+	    !wrmsr_safe(MSR_EFER,
+			header->pmode_efer_low,
+			header->pmode_efer_high))
 		header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER);
 #endif /* !CONFIG_64BIT */
 
@@ -61,7 +72,10 @@ int x86_acpi_suspend_lowlevel(void)
 	}
 	if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
 			&header->pmode_misc_en_low,
-			&header->pmode_misc_en_high))
+			&header->pmode_misc_en_high) &&
+	    !wrmsr_safe(MSR_IA32_MISC_ENABLE,
+			header->pmode_misc_en_low,
+			header->pmode_misc_en_high))
 		header->pmode_behavior |=
 			(1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
 	header->realmode_flags = acpi_realmode_flags;
--
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