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Date:	Mon, 15 Jul 2013 15:46:58 -0700
From:	Arjan van de Ven <arjan@...ux.intel.com>
To:	Peter Zijlstra <peterz@...radead.org>
CC:	Morten Rasmussen <morten.rasmussen@....com>, mingo@...nel.org,
	vincent.guittot@...aro.org, preeti@...ux.vnet.ibm.com,
	alex.shi@...el.com, efault@....de, pjt@...gle.com,
	len.brown@...el.com, corbet@....net, akpm@...ux-foundation.org,
	torvalds@...ux-foundation.org, tglx@...utronix.de,
	catalin.marinas@....com, linux-kernel@...r.kernel.org,
	linaro-kernel@...ts.linaro.org
Subject: Re: [RFC][PATCH 0/9] sched: Power scheduler design proposal


>> so depending of the mix of compute and memory instructions, different tradeoffs
>> might be needed.
>>
>> (for an example of this, AMD exposes a CPU counter for this as of recently and added
>> patches to "ondemand" to use it)
>
> OK, but isn't that part of why the micro controller might not make you go
> faster even if you do program a higher P state?
>
> But yes, I understand this issue in the 'traditional' cpufreq sense. There's no
> point in ramping the speed if all you do is stall more.
>
> But I was under the impression the 'hardware' was doing this. If not then we
> need the whole go-faster and go-slower thing and places to call them and means
> to determine to call them etc.

so the answer is "somewhat" and "on some cpus"
not all generations of Intel cpus are the same in this regard ;-(

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