linux-kernel - Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20130718133158.GA1628@arwen.pp.htv.fi>
Date:	Thu, 18 Jul 2013 16:31:58 +0300
From:	Felipe Balbi <balbi@...com>
To:	Mark Brown <broonie@...nel.org>
CC:	Sourav Poddar <sourav.poddar@...com>,
	<spi-devel-general@...ts.sourceforge.net>,
	<grant.likely@...aro.org>, <balbi@...com>, <rnayak@...com>,
	<linux-omap@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCHv4 2/3] drivers: spi: Add qspi flash controller

Hi,

On Thu, Jul 18, 2013 at 02:18:22PM +0100, Mark Brown wrote:
> > >>+static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
> > >>+{
> > >>+	struct ti_qspi *qspi = dev_id;
> > >>+	u16 mask, stat;
> > >>+
> > >>+	irqreturn_t ret = IRQ_HANDLED;
> > >>+
> > >>+	spin_lock(&qspi->lock);
> > >>+
> > >>+	stat = ti_qspi_readl(qspi, QSPI_SPI_STATUS_REG);
> > >>+	mask = ti_qspi_readl(qspi, QSPI_INTR_ENABLE_SET_REG);
> > >>+
> > >>+	if (stat&&  mask)
> > >>+		ret = IRQ_WAKE_THREAD;
> > >>+
> > >>+	spin_unlock(&qspi->lock);
> > >>+
> > >>+	return ret;
> 
> > >According to the above code we might interrupt for masked events...
> > >that's a bit worrying isn't it?
> 
> > Yes, there is WC interrupt enable bit which enables the interrupt.
> > This interrupt
> > gets disabled by writing to the CLEAR reg in the threaded irq.
> 
> So why do we report that we handled the interrupt then?  Shouldn't we at
> least warn if we're getting spurious IRQs?

not spurious. OMAP has two sets of IRQ status registers. One is call
IRQSTATUS$n (n = 0, 1, ...) and IRQSTATUS_RAW$n.

IRQSTATUS$n will only enable the bits which fired IRQs and aren't
masked while IRQSTATUS_RAW$n will also enable the bits which are masked.
I could never come up with a use case where we would need to handle IRQs
which we decided to mask, but perhaps there might be some cases, I don't
know.

Based on that, I believe Sourav is reading IRQSTATUS_RAW$n, then he need
to clear the masked bits.

-- 
balbi

Download attachment "signature.asc" of type "application/pgp-signature" (837 bytes)