linux-kernel - Re: [PATCH] ARM: perf: Implement perf_arch_fetch_caller

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Message-ID: <20130721213937.GB29879@mudshark.cambridge.arm.com>
Date:	Sun, 21 Jul 2013 22:39:37 +0100
From:	Will Deacon <will.deacon@....com>
To:	Jed Davis <jld@...illa.com>
Cc:	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Paul Mackerras <paulus@...ba.org>,
	Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	Russell King <linux@....linux.org.uk>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: perf: Implement perf_arch_fetch_caller_regs

On Sat, Jul 20, 2013 at 04:43:21AM +0100, Jed Davis wrote:
> On Mon, Jul 15, 2013 at 02:53:42PM +0100, Will Deacon wrote:
> > > +				     "mov %[_pc],  r15\n\t"		\
> > > +				     "mrs %[_cpsr], cpsr\n\t"		\
> > > +				     : [_cpsr] "=r" (_cpsr),		\
> > > +				       [_pc] "=r" (_pc)			\
> > > +				     : [_regs] "r" (&(regs)->uregs)	\
> > 
> > It would be cleaner to pass a separate argument for each register, using the
> > ARM_rN macros rather than calculating the offset by hand.
> 
> I'll do that.  If there were more arguments there might be a problem
> at -O0, because the naive translation can run out of registers in
> some cases, but that shouldn't be a problem here.  (Nor if someone
> later extends this to all the core registers, because {r0-r13} can and
> presumably should use a store-multiple.)

We already rely on compiler optimisation for things like tlbflush.h, so we
don't need to worry about building with -O0.

Please send a v2 when you get a chance!

Will
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