linux-kernel - Re: [PATCH] perf, x86: Enable PEBS mode automatically for mem-{loads,stores} v3

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Date:	Tue, 23 Jul 2013 19:46:14 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	Andi Kleen <andi@...stfloor.org>, Ingo Molnar <mingo@...nel.org>,
	LKML <linux-kernel@...r.kernel.org>,
	Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH] perf, x86: Enable PEBS mode automatically for
 mem-{loads,stores} v3

On Tue, Jul 23, 2013 at 6:57 PM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Tue, Jul 23, 2013 at 06:13:34PM +0200, Andi Kleen wrote:
>> On Tue, Jul 23, 2013 at 10:38:34AM +0200, Peter Zijlstra wrote:
>> > On Thu, Jul 18, 2013 at 04:03:39PM -0700, Andi Kleen wrote:
>> > > From: Andi Kleen <ak@...ux.intel.com>
>> > >
>> > > [The patch to enable this in the user tools has been sent separately]
>> > >
>> > > With the earlier patches to automatically try cpu// and add
>> > > a precise sys attribute, we can now enable PEBS for the mem-loads,
>> > > mem-stores events everywhere.
>> > >
>> > > This allows to use
>> > >
>> > > perf record -e mem-loads ...
>> > >
>> > > instead of
>> > >
>> > > perf record -e cpu/mem-loads/p ...
>> > >
>> > > Always use precise=2 even though it is costly pre-Haswell
>> >
>> > This Changelog fails to give a reason _why_ we'd want to do this.
>>
>> The first is much nicer to type and understand? Just in the spirit of
>> making perf easier to use.
>
> And here I was thinking that maybe these events don't make sense without
> pebs or so. But no, rather than giving an actual useful reason you'd
> have me look things up myself. *sigh*

The loads events using LATENCY_ABOVE_THRESHOLD do not count anything
without PEBS (that's for all processors pre-Haswell).

As for forcing precise=2, I think that is what people would expect,
i.e., point me
to the load/store instruction. Experts can still force precise=1 because I think
the parser uses the value of the last precise= instance.
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