linux-kernel - Re: [PATCH 1/4] ARM: dove: add cpu device tree node

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Message-ID: <51F677CB.4090100@gmail.com>
Date:	Mon, 29 Jul 2013 16:10:19 +0200
From:	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
To:	Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@....com>
CC:	Russell King <linux@....linux.org.uk>,
	Jason Cooper <jason@...edaemon.net>,
	Andrew Lunn <andrew@...n.ch>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Maen Suleiman <maen@...vell.com>,
	Lior Amsalem <alior@...vell.com>
Subject: Re: [PATCH 1/4] ARM: dove: add cpu device tree node

On 07/29/2013 02:41 PM, Sudeep KarkadaNagesha wrote:
> On 29/07/13 13:29, Sebastian Hesselbarth wrote:
>> This adds a node for the Marvell Sheeva PJ4A CPU found on Dove SoCs.
>> While at it, also move the l2-cache node out of internal registers and
>> consistently name different nodes.
>>
>> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
>> ---
>> Cc: Russell King <linux@....linux.org.uk>
>> Cc: Jason Cooper <jason@...edaemon.net>
>> Cc: Andrew Lunn <andrew@...n.ch>
>> Cc: linux-arm-kernel@...ts.infradead.org
>> Cc: devicetree@...r.kernel.org
>> Cc: linux-kernel@...r.kernel.org
>> ---
>>   arch/arm/boot/dts/dove.dtsi |   52 ++++++++++++++++++++++++++-----------------
>>   1 file changed, 32 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
>> index 8d5be1e8..09d9710 100644
>> --- a/arch/arm/boot/dts/dove.dtsi
>> +++ b/arch/arm/boot/dts/dove.dtsi
>> @@ -10,6 +10,23 @@
>>   		gpio2 = &gpio2;
>>   	};
>>
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu0: cpu@0 {
>> +			compatible = "marvell,pj4a", "marvell,sheeva-v7";
>> +			device_type = "cpu";
>> +			next-level-cache = <&l2>;
>> +			reg = <0>;
>> +		};
>> +	};
>> +
>> +	l2: l2-cache {
>> +		compatible = "marvell,tauros2-cache";
>> +		marvell,tauros2-cache-features = <0>;
>> +	};
> Hi Sebastian,
>
> This is not entirely related to the patch but thought of checking with
> you. I was trying to get info on L2 cache controller on Marvell SoCs,
> mainly structure or way/set size. Is that something we can get
> dynamically ? Some specification I referred said its integrated and some
> said its separate(not unified). Basically I need information around
> various L2 cache implementations(Tauros2/Feroceon) from Marvell.
>
> Any pointers or contacts to get this information will be helpful.

Sudeep,

I added Maen and Lior on Cc. Unfortunately, public Marvell SoC
datasheets only refer some closed Marvell datasheets when it comes
to CPU(s) used. Maybe they can help out.

Sebastian

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