Message-ID: <20130729172327.GA20592@e102568-lin.cambridge.arm.com>
Date:	Mon, 29 Jul 2013 18:23:27 +0100
From:	Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:	Dave Martin <Dave.Martin@....com>
Cc:	Will Deacon <Will.Deacon@....com>,
	Vincent Guittot <vincent.guittot@...aro.org>,
	"linaro-kernel@...ts.linaro.org" <linaro-kernel@...ts.linaro.org>,
	Graeme Gregory <graeme.gregory@...aro.org>,
	Al Stone <al.stone@...aro.org>,
	Patch Tracking <patches@...aro.org>,
	Catalin Marinas <Catalin.Marinas@....com>,
	linaro-acpi <linaro-acpi@...ts.linaro.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	Tomasz Nowicki <tomasz.nowicki@...aro.org>,
	Hanjun Guo <hanjun.guo@...aro.org>,
	Naresh Bhat <naresh.bhat@...aro.org>,
	Russell King <rmk+kernel@....linux.org.uk>,
	LAK <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [RFC][PATCH 1/2] ARM64: add cpu topology definition

On Mon, Jul 29, 2013 at 02:36:30PM +0100, Dave Martin wrote:
> On Mon, Jul 29, 2013 at 10:54:01AM +0100, Will Deacon wrote:
> > On Mon, Jul 29, 2013 at 10:46:06AM +0100, Vincent Guittot wrote:
> > > On 27 July 2013 12:42, Hanjun Guo <hanjun.guo@...aro.org> wrote:
> > > > Power aware scheduling needs the cpu topology information to improve the
> > > > cpu scheduler decision making.
> > > 
> > > It's not only power aware scheduling. The scheduler already uses
> > > topology and cache sharing when  CONFIG_SCHED_MC and/or
> > > CONFIG_SCHED_SMT are enable. So you should also add these configs for
> > > arm64 so the scheduler can use it
> > 
> > ... except that the architecture doesn't define what the AFF fields in MPIDR
> > really represent. Using them to make key scheduling decisions relating to
> 
> In fact, the ARM Architecture doesn't place any requirements on MPIDRs to
> force the aff fields to exist _at all_.  It's just a recommendation.
> Instead, you have a 24 or 32-bit number which is unique per CPU, and which
> is _probably_ assigned in a way resembling the aff fields.
> 
> > cache proximity seems pretty risky to me, especially given the track record
> > we've seen already on AArch32 silicon. It's a convenient register if it
> > contains the data we want it to contain, but we need to force ourselves to
> > come to terms with reality here and simply use it as an identifier for a
> > CPU.
> 
> +1
> 
> Also, we should align arm and arm64.  The problem is basically exactly
> the same, and the solution needs to be the same.  struct cputopo_arm is
> already being abused  -- for example, TC2 describes the A15 and A7
> clusters on a single die as having different "socket_id" values, even
> though this is obviously nonsense.  But there's no other way to describe
> that system today.
> 
> > Can't we just use the device-tree to represent this topological data for
> > arm64? Lorenzo has been working on bindings in this area.
> 
> This may become more important as we start to see things like asymmetric
> topologies appearing (different numbers of nodes and different
> interdependence characteristics in adjacent branches of the topology
> etc.)

Will and Dave summed up the existing issues with MPIDR definition related to
the topology description.

FYI, a link to the current topology bindings posted on DT-discuss and LAKML:

https://lists.ozlabs.org/pipermail/devicetree-discuss/2013-April/031725.html

I am waiting for the dust to settle on the DT bindings review discussions to
repost them and get them finalized.

Lorenzo

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