lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:	Tue, 30 Jul 2013 15:18:28 +0200
From:	Maxime Ripard <maxime.ripard@...e-electrons.com>
To:	Marc Zyngier <marc.zyngier@....com>
Cc:	Thomas Gleixner <tglx@...utronix.de>,
	Mike Turquette <mturquette@...aro.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	"albert.u.boot@...baud.net" <albert.u.boot@...baud.net>,
	Emilio Lopez <emilio@...pez.com.ar>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"shuge@...winnertech.com" <shuge@...winnertech.com>,
	"linux-sunxi@...glegroups.com" <linux-sunxi@...glegroups.com>,
	"kevin.z.m.zh@...il.com" <kevin.z.m.zh@...il.com>,
	"sunny@...winnertech.com" <sunny@...winnertech.com>,
	Olof Johansson <olof@...om.net>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 05/10] ARM: sunxi: Add Allwinner A31 DTSI

Hi Marc,

On Tue, Jul 30, 2013 at 09:59:02AM +0100, Marc Zyngier wrote:
> Hi Maxime,
> 
> On 23/07/13 23:25, Maxime Ripard wrote:
> > Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> > ---
> >  arch/arm/boot/dts/Makefile       |   3 +-
> >  arch/arm/boot/dts/sun6i-a31.dtsi | 155 +++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 157 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/arm/boot/dts/sun6i-a31.dtsi
> > 
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 641b3c9..1482533 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -210,7 +210,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
> >  	sun4i-a10-mini-xplus.dtb \
> >  	sun4i-a10-hackberry.dtb \
> >  	sun5i-a10s-olinuxino-micro.dtb \
> > -	sun5i-a13-olinuxino.dtb
> > +	sun5i-a13-olinuxino.dtb \
> > +	sun6i-a31-colombus.dtb
> >  dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
> >  	tegra20-iris-512.dtb \
> >  	tegra20-medcom-wide.dtb \
> > diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> > new file mode 100644
> > index 0000000..c6c19a9
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> > @@ -0,0 +1,155 @@
> > +/*
> > + * Copyright 2013 Maxime Ripard
> > + *
> > + * Maxime Ripard <maxime.ripard@...e-electrons.com>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/include/ "skeleton.dtsi"
> > +
> 
> [...]
> 
> > +		gic: interrupt-controller@...81000 {
> > +			compatible = "arm,cortex-a7-gic";
> > +			reg = <0x01c81000 0x1000>, <0x01c82000 0x100>;
> 
> Th Cortex A7 TRM indicates that its GIC has the virtualization
> extensions. You should reflect this in the binding (wider GICC range,
> GICH and GICV ranges, maintenance interrupt).
> 
> See
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464d/BGBJFJJA.html
> for details.

Thanks!

I'll add those to the v2.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Download attachment "signature.asc" of type "application/pgp-signature" (837 bytes)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ