linux-kernel - [35/84] ASoC: sglt5000: Fix SGTL5000_PLL_FRAC_DIV

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Message-ID: <lsq.1375276989.575804976@decadent.org.uk>
Date:	Wed, 31 Jul 2013 15:23:09 +0200
From:	Ben Hutchings <ben@...adent.org.uk>
To:	linux-kernel@...r.kernel.org, stable@...r.kernel.org
CC:	akpm@...ux-foundation.org, "Mark Brown" <broonie@...aro.org>,
	"Oskar Schirmer" <oskar@...ra.com>,
	"Fabio Estevam" <fabio.estevam@...escale.com>
Subject: [35/84] ASoC: sglt5000: Fix SGTL5000_PLL_FRAC_DIV_MASK

3.2.50-rc1 review patch.  If anyone has any objections, please let me know.

------------------

From: Fabio Estevam <fabio.estevam@...escale.com>

commit 5c78dfe87ea04b501ee000a7f03b9432ac9d008c upstream.

SGTL5000_PLL_FRAC_DIV_MASK is used to mask bits 0-10 (11 bits in total) of
register CHIP_PLL_CTRL, so fix the mask to accomodate all this bit range.

Reported-by: Oskar Schirmer <oskar@...ra.com>
Signed-off-by: Fabio Estevam <fabio.estevam@...escale.com>
Signed-off-by: Mark Brown <broonie@...aro.org>
Signed-off-by: Ben Hutchings <ben@...adent.org.uk>
---
 sound/soc/codecs/sgtl5000.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/sound/soc/codecs/sgtl5000.h
+++ b/sound/soc/codecs/sgtl5000.h
@@ -347,7 +347,7 @@
 #define SGTL5000_PLL_INT_DIV_MASK		0xf800
 #define SGTL5000_PLL_INT_DIV_SHIFT		11
 #define SGTL5000_PLL_INT_DIV_WIDTH		5
-#define SGTL5000_PLL_FRAC_DIV_MASK		0x0700
+#define SGTL5000_PLL_FRAC_DIV_MASK		0x07ff
 #define SGTL5000_PLL_FRAC_DIV_SHIFT		0
 #define SGTL5000_PLL_FRAC_DIV_WIDTH		11
 

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