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Message-ID: <51FB6027.6080808@ti.com>
Date: Fri, 2 Aug 2013 10:30:47 +0300
From: Roger Quadros <rogerq@...com>
To: Nishanth Menon <nm@...com>
CC: <tony@...mide.com>, <rnayak@...com>, <benoit.cousson@...aro.org>,
<balbi@...com>, <george.cherian@...com>, <kishon@...com>,
<dmurphy@...com>, <t-kristo@...com>, <linux-omap@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/4] CLK: ti: dra7: Initialize USB_DPLL
Hi Nishant,
On 08/01/2013 06:06 PM, Nishanth Menon wrote:
> On 08/01/2013 09:58 AM, Roger Quadros wrote:
>> USB_DPLL must be initialized and locked at boot so that
>> USB modules can work.
>>
>> Also program USB_DLL_M2 output to half rate.
>>
>> Signed-off-by: Roger Quadros <rogerq@...com>
>> ---
>> drivers/clk/omap/clk-7xx.c | 11 +++++++++++
>> 1 files changed, 11 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
>> index ddb39dd..f444513 100644
>> --- a/drivers/clk/omap/clk-7xx.c
>> +++ b/drivers/clk/omap/clk-7xx.c
>> @@ -19,6 +19,7 @@
>>
>> #define DRA7_DPLL_ABE_DEFFREQ 361267200
>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>> +#define DRA7_DPLL_USB_DEFFREQ 960000000
>>
>>
>> static struct omap_dt_clk dra7xx_clks[] = {
>> @@ -63,5 +64,15 @@ int __init dra7xx_clk_init(void)
>> if (rc)
>> pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
>>
>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
>> + if (rc)
>> + pr_err("%s: failed to configure USB DPLL!\n", __func__);
>> +
>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
>> + if (rc)
>> + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
>> +
>> return rc;
>> }
>>
> As I had mentioned on [1] - we are going to see similar needs keep popping up. there is no need to hack this up for even more peripherals :(
>
> http://marc.info/?l=linux-omap&m=137536803106017&w=2
>
The DPLLs need to be initialized irrespective of whether peripheral drivers are present or not.
We have seen cases where the SoC fails to enter RETention if the DPLLS are not correctly
configured.
But I agree with you that we should be able to initialize it by specifying the initial rate via Clock Data.
This patch can be removed when the appropriate feature is added in OMAP clock core.
cheers,
-roger
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