linux-kernel - Re: [PATCH v9 05/16] clk: exynos: add gate clock descriptions of System MMU

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Date:	Thu, 08 Aug 2013 13:40:13 +0200
From:	Tomasz Figa <t.figa@...sung.com>
To:	Sylwester Nawrocki <s.nawrocki@...sung.com>
Cc:	Cho KyongHo <pullip.cho@...sung.com>,
	'Linux ARM Kernel' <linux-arm-kernel@...ts.infradead.org>,
	'Linux IOMMU' <iommu@...ts.linux-foundation.org>,
	'Linux Kernel' <linux-kernel@...r.kernel.org>,
	'Linux Samsung SOC' <linux-samsung-soc@...r.kernel.org>,
	devicetree@...r.kernel.org, 'Joerg Roedel' <joro@...tes.org>,
	'Kukjin Kim' <kgene.kim@...sung.com>,
	'Prathyush' <prathyush.k@...sung.com>,
	'Rahul Sharma' <rahul.sharma@...sung.com>,
	'Subash Patel' <supash.ramaswamy@...aro.org>,
	'Grant Grundler' <grundler@...omium.org>,
	'Antonios Motakis' <a.motakis@...tualopensystems.com>,
	kvmarm@...ts.cs.columbia.edu,
	'Sachin Kamat' <sachin.kamat@...aro.org>
Subject: Re: [PATCH v9 05/16] clk: exynos: add gate clock descriptions of
 System MMU

On Thursday 08 of August 2013 13:17:34 Sylwester Nawrocki wrote:
> On 08/08/2013 11:38 AM, Cho KyongHo wrote:
> > This adds gate clocks of all System MMUs and their master IPs
> > that are not apeared in clk-exynos5250.c
> > Also fixes GATE_IP_ACP to 0x18800 and changed GATE_DA to GATE
> > for System MMU clocks in clk-exynos4.c
> > 
> > Signed-off-by: Cho KyongHo <pullip.cho@...sung.com>
> > ---
> > 
> >  .../devicetree/bindings/clock/exynos5250-clock.txt |   26 +++++++++
> >  drivers/clk/samsung/clk-exynos4.c                  |   27 +++------
> >  drivers/clk/samsung/clk-exynos5250.c               |   57
> >  ++++++++++++++++---- 3 files changed, 82 insertions(+), 28
> >  deletions(-)
> 
> [...]
> 
> > @@ -349,19 +358,26 @@ static struct samsung_gate_clock
> > exynos5250_gate_clks[] __initdata = {> 
> >  	GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
> >  	GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
> >  	GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
> > 
> > -	GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
> > -	GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
> > -	GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
> > -	GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
> > +	GATE(smmu_gscl0, "smmu_gscl0", "none", GATE_IP_GSCL, 7, 0, 0),
> > +	GATE(smmu_gscl1, "smmu_gscl1", "none", GATE_IP_GSCL, 8, 0, 0),
> > +	GATE(smmu_gscl2, "smmu_gscl2", "none", GATE_IP_GSCL, 9, 0, 0),
> > +	GATE(smmu_gscl3, "smmu_gscl3", "none", GATE_IP_GSCL, 10, 0, 0),
> 
> Why are the smmu clocks' parent clocks removed ? Shouldn't both the
> gscaler gate clock and the gscaler smmu clock be still same, as it is in
> case of exynos4 ?

I agree with Sylwester.

In fact, it is not a valid clock setup. A valid clock must be either root 
clock (indicated by appropriate clock flag and specified frequency) or have 
a valid parent.

Best regards,
Tomasz

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