linux-kernel - [PATCH 07/18] dmaengine: PL08x: Fix reading the byte count in cctl

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Message-Id: <1376243970-6489-8-git-send-email-tomasz.figa@gmail.com>
Date:	Sun, 11 Aug 2013 19:59:19 +0200
From:	Tomasz Figa <tomasz.figa@...il.com>
To:	linux-samsung-soc@...r.kernel.org
Cc:	linux-arm-kernel@...ts.infradead.org, alsa-devel@...a-project.org,
	linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org,
	Dan Williams <djbw@...com>, Jaroslav Kysela <perex@...ex.cz>,
	Kukjin Kim <kgene.kim@...sung.com>,
	Liam Girdwood <lgirdwood@...il.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	Mark Brown <broonie@...nel.org>,
	Mike Turquette <mturquette@...aro.org>,
	Padmavathi Venna <padma.v@...sung.com>,
	Russell King <linux@....linux.org.uk>,
	Sangbeom Kim <sbkim73@...sung.com>,
	Takashi Iwai <tiwai@...e.de>,
	Vinod Koul <vinod.koul@...el.com>,
	Alban Bedel <alban.bedel@...onic-design.de>,
	Tomasz Figa <tomasz.figa@...il.com>
Subject: [PATCH 07/18] dmaengine: PL08x: Fix reading the byte count in cctl

From: Alban Bedel <alban.bedel@...onic-design.de>

There are more fields than just SWIDTH in CH_CONTROL register, so read
register value must be masked in addition to shifting.

Signed-off-by: Alban Bedel <alban.bedel@...onic-design.de>
Signed-off-by: Tomasz Figa <tomasz.figa@...il.com>
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>
---
 drivers/dma/amba-pl08x.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 4e4c3df..6b9cba2 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -480,6 +480,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
@@ -498,6 +500,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
 	/* The source width defines the number of bytes */
 	u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 
+	cctl &= PL080_CONTROL_SWIDTH_MASK;
+
 	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
 	case PL080_WIDTH_8BIT:
 		break;
-- 
1.8.3.2

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