linux-kernel - Re: [PATCH] PCI: exynos: add support for MSI

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Message-ID: <CAK9yfHwEPEfhMCWGbDWK2NQE2zAgmsQc6_Dn498pRP4UX6sYmQ@mail.gmail.com>
Date:	Mon, 12 Aug 2013 14:42:31 +0530
From:	Sachin Kamat <sachin.kamat@...aro.org>
To:	Jingoo Han <jg1.han@...sung.com>
Cc:	Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
	linux-samsung-soc@...r.kernel.org,
	Kukjin Kim <kgene.kim@...sung.com>,
	Pratyush Anand <pratyush.anand@...com>,
	Mohit KUMAR <Mohit.KUMAR@...com>,
	Siva Reddy Kallam <siva.kallam@...sung.com>,
	SRIKANTH TUMKUR SHIVANAND <ts.srikanth@...sung.com>,
	Arnd Bergmann <arnd@...db.de>, Sean Cross <xobs@...agi.com>,
	Kishon Vijay Abraham I <kishon@...com>,
	Thierry Reding <thierry.reding@...il.com>,
	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH] PCI: exynos: add support for MSI

Hi Jingoo,

On 12 August 2013 14:26, Jingoo Han <jg1.han@...sung.com> wrote:
> This patch adds support for Message Signaled Interrupt in the
> Exynops PCIe diver using Synopsys designware PCIe core IP.

s/Exynops PCIe diver/Exynos PCIe driver

>
> Signed-off-by: Siva Reddy Kallam <siva.kallam@...sung.com>
> Signed-off-by: Srikanth T Shivanand <ts.srikanth@...sung.com>
> Signed-off-by: Jingoo Han <jg1.han@...sung.com>
> Cc: Pratyush Anand <pratyush.anand@...com>
> Cc: Mohit KUMAR <Mohit.KUMAR@...com>
> ---
>  arch/arm/boot/dts/exynos5440.dtsi  |    2 +
>  arch/arm/mach-exynos/Kconfig       |    1 +
>  drivers/pci/host/pci-exynos.c      |   60 ++++++++++
>  drivers/pci/host/pcie-designware.c |  213 ++++++++++++++++++++++++++++++++++++
>  drivers/pci/host/pcie-designware.h |    8 ++
>  5 files changed, 284 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
> index 586134e..3746835 100644
> --- a/arch/arm/boot/dts/exynos5440.dtsi
> +++ b/arch/arm/boot/dts/exynos5440.dtsi
> @@ -249,6 +249,7 @@
>                 interrupt-map-mask = <0 0 0 0>;
>                 interrupt-map = <0x0 0 &gic 53>;
>                 num-lanes = <4>;
> +               msi-base = <200>;

Please update the bindings documentation too.

>         };
>
>         pcie@...000 {
> @@ -269,5 +270,6 @@
[snip]
>
> +#ifdef CONFIG_PCI_MSI
> +static void exynos_pcie_clear_irq_level(struct pcie_port *pp)
> +{
> +       u32 val;
> +       struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
> +       void __iomem *elbi_base = exynos_pcie->elbi_base;
> +
> +       val = readl(elbi_base + PCIE_IRQ_LEVEL);
> +       writel(val, elbi_base + PCIE_IRQ_LEVEL);

Sorry, I did not get this. Writing the value read from the same
register without any operation.

-- 
With warm regards,
Sachin
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