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Message-ID: <1377703127-7020-2-git-send-email-ttynkkynen@nvidia.com>
Date: Wed, 28 Aug 2013 18:18:47 +0300
From: Tuomas Tynkkynen <ttynkkynen@...dia.com>
To: <mturquette@...aro.org>
CC: <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<swarren@...dotorg.org>, <linux-usb@...r.kernel.org>,
Tuomas Tynkkynen <ttynkkynen@...dia.com>
Subject: [PATCH 2nd RESEND] clk: tegra30: Don't wait for PLL_U lock bit
The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@...dia.com>
Tested-by: Stephen Warren <swarren@...dia.com>
Acked-by: Stephen Warren <swarren@...dia.com>
---
drivers/clk/tegra/clk-tegra30.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index e2c6ca0..9103fc8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -971,7 +971,7 @@ static void __init tegra30_pll_init(void)
/* PLLU */
clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
- TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK,
+ TEGRA_PLL_SET_LFCON,
pll_u_freq_table,
NULL);
clk_register_clkdev(clk, "pll_u", NULL);
--
1.8.1.5
--
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