linux-kernel - Re: [RFC PATCH 1/4] DRIVERS: IRQCHIP: Add crossbar irqchip driver

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Message-ID: <alpine.DEB.2.02.1309131142540.4089@ionos.tec.linutronix.de>
Date:	Fri, 13 Sep 2013 16:24:29 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Santosh Shilimkar <santosh.shilimkar@...com>
cc:	Sricharan R <r.sricharan@...com>,
	LKML <linux-kernel@...r.kernel.org>, devicetree@...r.kernel.org,
	linux-doc@...r.kernel.org,
	LAK <linux-arm-kernel@...ts.infradead.org>,
	linux-omap@...r.kernel.org, linus.walleij@...aro.org,
	Russell King <linux@....linux.org.uk>,
	Tony Lindgren <tony@...mide.com>, rnayak@...com
Subject: Re: [RFC PATCH 1/4] DRIVERS: IRQCHIP: Add crossbar irqchip driver

On Thu, 12 Sep 2013, Santosh Shilimkar wrote:
> On Thursday 12 September 2013 08:26 PM, Thomas Gleixner wrote:
> > Let me summarize:
> > 
> >    - GIC supports up to 160 interrupts
> > 
> >    - CROSSBAR supports up to 250 interrupts 
> > 
> >    - CROSSBAR routes up to 160 out of 250 interrupts to the GIC ones
> > 
> >    - Drivers request a CROSSBAR interrupt number which must be mapped
> >      to some arbitrary available GIC irq number
> > 
> Correct.
> 
> > So basically the CROSSBAR mechanism is pretty much the same as MSI[X]
> > just in a different flavour and with a different set of semantics and
> > limitations, i.e. poor mans MSI[X] with a new level of bogosity.
> > 
> > So if CROSSBAR is going to be the new fangled SoC MSI[X] long term
> > equivalent then you better provide some infrastructure for that and
> > make the drivers ready to use it. Maybe check with the PCI/MSI folks
> > to share some of the interfaces.
> >
> > If that whole thing is another onetime HW designers wet dream, then
> > please go back to the limited but completely functional (Who is going
> > to use more than 160 peripheral interrupts????) device tree model. I
> > really have no interest to support hardware designer brain farts.
> > 
> Thanks for clear NAK for irqchip approach. I should have looped you
> in the discussion where I was also suggesting against the irqchip
> approach. We will try to look at MSI stuff but if its get too
> complicated am going to fall-back to the initial probe based
> approach to achieve the functionality.

Before you dig into MSI, lets talk about irq domains first.

GIC implements a legacy irq domain, i.e. a linear domain of all
possible GIC interrupts with a 1:1 mapping.

So why can't you make use of irq domains and have the whole routing
business implemented sanely?

What's needed is in gic_init_bases():

       if (of_property_read(node, "routable_irqs", &nr_routable_irqs) {
       	  irq_domain_add_legacy(nr_gic_irqs);
       } else {
       	  irq_domain_add_legacy(nr_per_cpu_irqs);
	  irq_domain_add_linear(nr_routable_irqs);
       }

Now that separate domain has an xlate function which grabs a free GIC
irq from a bitmap and returns the hardware irq number in the gic
space. The map/unmap callbacks take care of setting up / tearing down
the route in the crossbar.

Thoughts?

Thanks,

	tglx
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