lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <CAK3cCBzSnDgJ1km72UwFQ9RK3ccJMB=bgHzSvC0P_R75KzcDYw@mail.gmail.com>
Date:	Wed, 18 Sep 2013 17:03:10 +0800
From:	cinifr <cinifr@...il.com>
To:	Marc Zyngier <marc.zyngier@....com>
Cc:	Mark Rutland <Mark.Rutland@....com>,
	"coosty@....com" <coosty@....com>,
	"maxime.ripard@...e-electrons.com" <maxime.ripard@...e-electrons.com>,
	"daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"tglx@...utronix.de" <tglx@...utronix.de>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"rob.herring@...xeda.com" <rob.herring@...xeda.com>,
	"linux-sunxi@...glegroups.com" <linux-sunxi@...glegroups.com>
Subject: Re: [PATCH 3/4] Add physical count arch timer support for clocksource
 in ARMv7.

HI all,
      I have modified uboot code to switch monitor mode and to set
cntvoff for all smp cpus for allwinner a20 cpu. It works, kernel can
run ok without using cntpct. I will commit the path for uboot after
reviewing the code.
      Rong


On 13 September 2013 21:40, Marc Zyngier <marc.zyngier@....com> wrote:
> On 13/09/13 14:09, cinifr wrote:
>>> I urge you to read the ARM ARM, and specifically the section dedicated
>>> to trapping access to CP15 operations. If you do, you'll quickly notice
>>> that you *cannot* trap accesses to the timer subsystem.
>>>
>> I read it again. The ARMv7 manual said "Is accessible from Non-secure
>> PL1 modes only when CNTHCTL.PL1PCTEN is set to 1. When
>> CNTHCTL.PL1PCTEN is set to 0, any attempt to access CNTPCT from a
>> Non-secure PL1 mode ***generates a Hyp Trap exception***, see Hyp Trap
>> exception on page B1-1206" in B8.1.2. but I dont find  a  special hyp
>> trap control  for accessing CNTPCT in manual. As you said HSTR cannot
>> trap accessing of CP15 c14. What happer when OS access CNTPCT from PL1
>> NS=1 mode with CNTHCTL.PL1PCTEN=0 ???  AmI  wrong for understanding
>> the manual?
>
> That's interesting, as I never noticed this particular line in the ARM
> ARM. I'll investigate this, thanks for bringing it up.
>
> This doesn't change the fact that using the physical timer/counter in a
> VM is (or can be) horribly expensive, and should be avoided at all cost.
>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny...
>
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ