linux-kernel - Re: [PATCH] usb: dwc3: core: clarify usb-phy array binding

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Message-ID: <20130918142118.GJ21559@radagast>
Date:	Wed, 18 Sep 2013 09:21:18 -0500
From:	Felipe Balbi <balbi@...com>
To:	Mark Rutland <mark.rutland@....com>
CC:	Felipe Balbi <balbi@...com>, Kumar Gala <galak@...eaurora.org>,
	"rob.herring@...xeda.com" <rob.herring@...xeda.com>,
	Pawel Moll <Pawel.Moll@....com>,
	Stephen Warren <swarren@...dotorg.org>,
	Ian Campbell <ian.campbell@...rix.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] usb: dwc3: core: clarify usb-phy array binding

Hi,

On Wed, Aug 28, 2013 at 05:01:51PM +0100, Mark Rutland wrote:
> > > So it's not physically possible for someone to just wire up a single phy
> > > to the device, either USB2-only or USB3?
> > 
> > of course it is :-) In fact, TI has done it. But it causes a whole bunch
> > of other problems to support that sort of model. For one, in some
> > systems, a clock generated by the USB3 PHY is backfed into the IP and if
> > USB3 PHY isn't running, the dwc3 IP won't start.
> 
> That sounds like a mess. But unless I've misunderstood, that doesn't

well, it is :-)

> sound like a general problem with having one phy, but rather an
> integration issue on a specific system? Presumably in that case as long
> as the phy was brought up before poking the rest of the IP, the unit
> would function correctly.

right, but what 'brings up' the PHY is usb_phy_init(). If we don't add
usb3phy to DTS or skip usb3phy in case maximum-speed < superspeed, then
we're screwed :-)

> > I even wrote a patch making USB3 PHY optional, but didn't push it
> > exactly because it broke some other systems and I can't guarantee users
> > won't mess up their DTS/pdata.
> 
> Does that mean that their dts or pdata are wrong at the moment, but
> they're spared because the driver bails out due to a missing phy? If
> their pdata's wrong, that should be fixable relatively easily, but if
> the dt is wrong then I'm not sure how we can support those systems
> sensibly. That sounds like an ideal candidate for a dt quirks
> mechanism...

hmm, the idea of the patch was:

	switch (maximum-speed) {
	case SUPER:
		grab_and_initialize_usb3_phy();
		grab_and_initialize_usb2_phy();
		break;
	case HIGH:
	case FULL:
	case LOW:
		grab_and_initialize_usb2_phy();
		break;
	}

now, imagine someone wants to run his dwc3 in highspeed mode, we
wouldn't initialize USB3 PHY which could cause the whole IP to break.

I tried poking around on device's registers to see if there was any way
to detect that the IP needs somethin back from USB3 PHY, but couldn't
find anything.

Since we can't know how the IP was integrated, it's best to leave it
alone and require NOP xceiv to be used.

> > > You can describe the USB2-only case in the dt by only listing the first
> > > phy (though the driver won't support it as it expects both to be
> > > present), but it's impossible to describe that you've wired up a single
> > > phy that's USB3 capable.
> > 
> > you might be right there...
> 
> Would it be possible to have something like (an optional) usb-phy-names?
> If not present, we assume the current situation, if present then we use
> it to figure out which phys are present. Maybe I'm missing something
> that makes that impossible?

you're missing the point regarding the IP possibly needing something
back from the PHY (e.g. a clock which PHY generates).

-- 
balbi

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