linux-kernel - Re: [PATCH v4 1/3] usb: dwc3: msm: Add device tree binding information

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Message-ID: <20130923193148.GN30811@radagast>
Date:	Mon, 23 Sep 2013 14:31:48 -0500
From:	Felipe Balbi <balbi@...com>
To:	"Ivan T. Ivanov" <iivanov@...sol.com>
CC:	<balbi@...com>, <rob.herring@...xeda.com>, <pawel.moll@....com>,
	<mark.rutland@....com>, <swarren@...dotorg.org>,
	<ian.campbell@...rix.com>, <rob@...dley.net>,
	<gregkh@...uxfoundation.org>, <grant.likely@...aro.org>,
	<idos@...eaurora.org>, <mgautam@...eaurora.org>,
	<devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <linux-usb@...r.kernel.org>,
	<linux-omap@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
	Andrew Morton <akpm@...ux-foundation.org>
Subject: Re: [PATCH v4 1/3] usb: dwc3: msm: Add device tree binding
 information

Hi,

On Tue, Aug 20, 2013 at 12:56:03PM +0300, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov" <iivanov@...sol.com>
> 
> MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
> (SNPS) and HS, SS PHY's control and configuration registers.
> 
> It could operate in device mode (SS, HS, FS) and host
> mode (SS, HS, FS, LS).
> 
> Signed-off-by: Ivan T. Ivanov <iivanov@...sol.com>

Any acks for the DT part ? This patch has been pending forever.

> ---
>  .../devicetree/bindings/usb/msm-ssusb.txt          |  104 ++++++++++++++++++++
>  1 file changed, 104 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/msm-ssusb.txt
> 
> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> new file mode 100644
> index 0000000..cacbd3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
> @@ -0,0 +1,104 @@
> +MSM SuperSpeed DWC3 USB SoC controller
> +
> +
> +DWC3 Highspeed USB PHY
> +======================
> +Required properities :
> +- compatible : sould be "qcom,dwc3-hsphy";
> +- reg : offset and length of the register set in the memory map
> +- clocks : phandles to clock instances of the device tree nodes
> +- clock-names :
> +	"xo" : External reference clock 19 MHz
> +	"sleep_a" : Sleep clock, used when USB3 core goes into low
> +	power mode (U3).
> +<supply-name>-supply : phandle to the regulator device tree node
> +Required "supply-name" are:
> +	"v1p8" : 1.8v supply for HSPHY
> +	"v3p3" : 3.3v supply for HSPHY
> +	"vbus" : vbus supply for host mode
> +	"vddcx" : vdd supply for HS-PHY digital circuit operation
> +
> +DWC3 Superspeed USB PHY
> +=======================
> +Required properities :
> +- compatible : sould be "qcom,dwc3-ssphy";
> +- reg : offset and length of the register set in the memory map
> +- clocks : phandles to clock instances of the device tree nodes
> +- clock-names :
> +	"xo" : External reference clock 19 MHz
> +	"ref" : Reference clock - used in host mode.
> +<supply-name>-supply : phandle to the regulator device tree node
> +Required "supply-name" are:
> +	"v1p8" : 1.8v supply for SS-PHY
> +	"vddcx" : vdd supply for SS-PHY digital circuit operation
> +
> +DWC3 controller wrapper
> +=======================
> +Required properties :
> +- compatible : should be "qcom,dwc3"
> +- reg : offset and length of the register set in the memory map
> +	offset and length of the TCSR register for routing USB
> +	signals to either picoPHY0 or picoPHY1.
> +- clocks : phandles to clock instances of the device tree nodes
> +- clock-names :
> +	"core" : Master/Core clock, have to be >= 125 MHz for SS
> +	operation and >= 60MHz for HS operation
> +	"iface" : System bus AXI clock
> +	"sleep" : Sleep clock, used when USB3 core goes into low
> +	power mode (U3).
> +	"utmi" : Generated by HS-PHY. Used to clock the low power
> +	parts of thr HS Link layer.
> +Optional properties :
> +- gdsc-supply : phandle to the globally distributed switch controller
> +  regulator node to the USB controller.
> +Required child node:
> +A child node must exist to represent the core DWC3 IP block. The name of
> +the node is not important. The content of the node is defined in dwc3.txt.
> +
> +Example device nodes:
> +
> +	dwc3_hsphy: phy@...f8800 {
> +		compatible = "qcom,dwc3-hsphy";
> +		reg = <0xf92f8800 0x30>;
> +
> +		clocks = <&cxo>, <&usb2a_phy_sleep_cxc>;
> +		clock-names = "xo", "sleep_a";
> +
> +		vbus-supply = <&supply>;
> +		vddcx-supply = <&supply>;
> +		v1p8-supply = <&supply>;
> +		v3p3-supply = <&supply>;
> +	};
> +
> +	dwc3_ssphy: phy@...f8830 {
> +		compatible = "qcom,dwc3-ssphy";
> +		reg = <0xf92f8830 0x30>;
> +
> +		clocks = <&cxo>, <&usb30_mock_utmi_cxc>;
> +		clock-names = "xo", "ref";
> +
> +		vddcx-supply = <&supply>;
> +		v1p8-supply = <&supply>;
> +	};
> +
> +	usb@...ab000 {
> +		compatible = "qcom,dwc3";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xfd4ab000 0x4>;
> +
> +		clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>,
> +				<&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>;
> +		clock-names = "core", "iface", "sleep", "utmi";
> +
> +		gdsc-supply = <&supply>;
> +
> +		ranges;
> +		dwc3@...00000 {
> +			compatible = "snps,dwc3";
> +			reg = <0xf9200000 0xcd00>;
> +			interrupts = <0 131 0>;
> +			usb-phy = <&dwc3_hsphy>, <&dwc3_ssphy>;
> +			tx-fifo-resize;
> +		};
> +	};
> -- 
> 1.7.9.5
> 

-- 
balbi

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