linux-kernel - Re: [PATCH v2 2/3] i2c: xilinx: Set tx direction in write operation

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Fri, 04 Oct 2013 11:53:49 +0200
From:	Michal Simek <monstr@...str.eu>
To:	Wolfram Sang <wsa@...-dreams.de>
CC:	Michal Simek <michal.simek@...inx.com>,
	linux-kernel@...r.kernel.org,
	Kedareswara rao Appana <appana.durga.rao@...inx.com>,
	Kedareswara rao Appana <appanad@...inx.com>,
	Jean Delvare <khali@...ux-fr.org>,
	Peter Korsgaard <jacmet@...site.dk>, linux-i2c@...r.kernel.org
Subject: Re: [PATCH v2 2/3] i2c: xilinx: Set tx direction in write operation

On 10/04/2013 07:46 AM, Wolfram Sang wrote:
> 
>> +	cr = xiic_getreg32(i2c, XIIC_CR_REG_OFFSET);
>> +	cr |= XIIC_CR_DIR_IS_TX_MASK;
>> +	xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, cr);
>> +
> 
> Is there no need to clear the bit again when receiving?

This bit is cleared in xiic_xfer() -> xiic_start_xfer() ->xiic_reinit()

xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);

> And did
> transferring ever work if this bit was never set before?

I really don't know. We have switched from old driver to this new mainline one
and based on our eeprom testing we have found that this bit hasn't been setup properly.

It is described here.
http://www.xilinx.com/support/documentation/ip_documentation/axi_iic/v1_02_a/axi_iic_ds756.pdf
page 28 - step 3.

IIC Master Transmitter with a Repeated Start
1. Write the IIC device address to the TX_FIFO.
2. Write data to TX_FIFO.
3. Write to Control Register (CR) to set MSMS = 1 and TX = 1.
4. Continue writing data to TX_FIFO.
5. Wait for transmit FIFO empty interrupt. This implies the IIC has throttled the bus.
6. Write to CR to set RSTA = 1.
7. Write IIC device address to TX_FIFO.
8. Write all data except last byte to TX_FIFO.
9. Wait for transmit FIFO empty interrupt. This implies the IIC has throttled the bus.
10. Write to CR to set MSMS = 0. The IIC generates a stop condition at the end of the last byte.
11. Write last byte of data to TX_FIFO.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform

Download attachment "signature.asc" of type "application/pgp-signature" (264 bytes)